公开(公告)号：US08495286B2

公开(公告)日：2013-07-23

申请号：US12962774

申请日：2010-12-08

申请人： Cagri Balkesen ,  Markus Buehler ,  Rainer Dorsch ,  Guenther Hutzl ,  Michael W. Kaufmann ,  Daniel Pfefferkorn ,  David Rohr ,  Stefanie Scherzinger ,  Thomas Schwarz

发明人： Cagri Balkesen ,  Markus Buehler ,  Rainer Dorsch ,  Guenther Hutzl ,  Michael W. Kaufmann ,  Daniel Pfefferkorn ,  David Rohr ,  Stefanie Scherzinger ,  Thomas Schwarz

IPC分类号： G06F12/00 ,  G06F3/00

CPC分类号： G06F12/0804 ,  G06F12/0215 ,  G06F12/0897 ,  Y02D10/13

摘要： The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.

摘要翻译： 本发明涉及用于操作DRAM主存储器的方法和相应的系统。 为多页提供一条缓冲线。 当向缓冲器写入数据时，根据其目的主存储器地址确定数据被写入哪个缓冲行。 存储由较低内存地址和数据组成的元组。 输入缓冲线的数据将按页进行排序，以防线路被刷新到主存储器。 对缓冲区条目进行排序会导致更少的页面打开和关闭，因为数据由存储器地址重新排列，因此以逻辑顺序排列。 通过对多个页面使用一行，只需要一个共同的组相关高速缓存的一部分存储器，从而显着地减少了开销。

公开(公告)号：US20110302367A1

公开(公告)日：2011-12-08

申请号：US12962774

申请日：2010-12-08

申请人： Cagri Balkesen ,  Markus Buehler ,  Rainer Dorsch ,  Guenther Hutzl ,  Michael W. Kaufmann ,  Daniel Pfefferkorn ,  David Rohr ,  Stefanie Scherzinger ,  Thomas Schwarz

发明人： Cagri Balkesen ,  Markus Buehler ,  Rainer Dorsch ,  Guenther Hutzl ,  Michael W. Kaufmann ,  Daniel Pfefferkorn ,  David Rohr ,  Stefanie Scherzinger ,  Thomas Schwarz

IPC分类号： G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/0215 ,  G06F12/0897 ,  Y02D10/13

摘要： The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.

摘要翻译： 本发明涉及用于操作DRAM主存储器的方法和相应的系统。 为多页提供一条缓冲线。 当向缓冲器写入数据时，根据其目的主存储器地址确定数据被写入哪个缓冲行。 存储由较低内存地址和数据组成的元组。 输入缓冲线的数据将按页进行排序，以防线路被刷新到主存储器。 对缓冲区条目进行排序会导致更少的页面打开和关闭，因为数据由存储器地址重新排列，因此以逻辑顺序排列。 通过对多个页面使用一行，只需要一个共同的组相关高速缓存的一部分存储器，从而显着地减少了开销。

公开(公告)号：US08380737B2

公开(公告)日：2013-02-19

申请号：US13233095

申请日：2011-09-15

申请人： Cagri Balkesen ,  Markus T. Buehler ,  Rainer Dorsch ,  Guenther Hutzl ,  Michael W. Kaufmann ,  Daniel Pfefferkorn ,  David Rohr ,  Stefanie C. Scherzinger ,  Thomas Schwarz

发明人： Cagri Balkesen ,  Markus T. Buehler ,  Rainer Dorsch ,  Guenther Hutzl ,  Michael W. Kaufmann ,  Daniel Pfefferkorn ,  David Rohr ,  Stefanie C. Scherzinger ,  Thomas Schwarz

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： G06F17/10 ,  G06F7/02 ,  G06F17/30952

摘要： First and second sets of numbers are received in an input range, which is separated into sub ranges. A first sub range is processed by initializing bits of a memory to a first logical state and by changing the initial state of each of the bits corresponding to a received number of the first set that is within the first sub range. Each number received in the second set is compared to a bit in the memory to identify a set of received numbers that are in the first sub range and that are in both the first set and the second set. The comparing is responsive to detecting a change of initial state of any bit in the memory during the processing of the first sub range. The processing and comparing is repeated for remaining sub ranges to identify received numbers that are in both the sets.

摘要翻译： 在输入范围内接收第一和第二组数字，分成子范围。 通过将存储器的位初始化为第一逻辑状态并且通过改变与在第一子范围内的第一集合的接收号码相对应的每个位的初始状态来处理第一子范围。 将第二组中接收到的每个数字与存储器中的位进行比较，以识别处于第一子范围并且处于第一集合和第二集合中的一组接收号码。 该比较响应于在第一子范围的处理期间检测存储器中任何位的初始状态的变化。 对于剩余子范围重复处理和比较以识别两个集合中的接收数字。

公开(公告)号：US20080216042A1

公开(公告)日：2008-09-04

申请号：US12032728

申请日：2008-02-18

申请人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

发明人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

摘要： A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

摘要翻译： 一种用于设计具有给定的目标到达时间窗口的一组信宿中的电子电路，特别是时钟树和子时钟树的方法和程序，优选地在集成电路上。 时钟树和子时钟树优选通过一个或多个固定电路来连接，这些电路不能被改变，克隆或去除。 构建至少一个逻辑结构的几个替代实施方案，并且为了存储数据的几个备选实现中的每一个。 构建一组配置，每个配置包括一个或多个替代实现的组合，并且每个配置满足完整集合集合处的目标到达时间窗口。 根据用于构造配置的数据（优选等待时间数据）的评估来选择配置。 不需要手动交互，并提供具有最小延迟的配置。

公开(公告)号：US07844931B2

公开(公告)日：2010-11-30

申请号：US12032728

申请日：2008-02-18

申请人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

发明人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

摘要： A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

摘要翻译： 一种用于设计具有给定的目标到达时间窗口的一组信宿中的电子电路，特别是时钟树和子时钟树的方法和程序，优选地在集成电路上。 时钟树和子时钟树优选通过一个或多个固定电路来连接，这些电路不能被改变，克隆或去除。 构建至少一个逻辑结构的几个替代实施方案，并且为了存储数据的几个备选实现中的每一个。 构建一组配置，每个配置包括一个或多个替代实现的组合，并且每个配置满足完整集合集合处的目标到达时间窗口。 根据用于构造配置的数据（优选等待时间数据）的评估来选择配置。 不需要手动交互，并提供具有最小延迟的配置。

公开(公告)号：US20080216043A1

公开(公告)日：2008-09-04

申请号：US12032734

申请日：2008-02-18

申请人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

发明人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

摘要： A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

摘要翻译： 一种设计结构，用于设计具有给定目标到达时间窗口的一组接收器内的电子电路，特别是时钟树和子时钟树，优选地在由IC设计公司或其他电路设计提供商设计的集成电路上。 时钟树和子时钟树优选通过一个或多个固定电路来连接，这些电路不能被改变，克隆或去除。 构建至少一个逻辑结构的几个替代实施方案，并且为了存储数据的几个备选实现中的每一个。 构建一组配置，每个配置包括一个或多个替代实现的组合，并且每个配置满足完整集合集合处的目标到达时间窗口。 根据用于构造配置的数据（优选等待时间数据）的评估来选择配置。 不需要手动交互，并提供具有最小延迟的配置。

公开(公告)号：US07886245B2

公开(公告)日：2011-02-08

申请号：US12032734

申请日：2008-02-18

申请人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

发明人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

摘要： A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

摘要翻译： 一种设计结构，用于设计具有给定目标到达时间窗口的一组接收器内的电子电路，特别是时钟树和子时钟树，优选地在由IC设计公司或其他电路设计提供商设计的集成电路上。 时钟树和子时钟树优选通过一个或多个固定电路来连接，这些电路不能被改变，克隆或去除。 构建至少一个逻辑结构的几个替代实施方案，并且为了存储数据的几个备选实现中的每一个。 构建一组配置，每个配置包括一个或多个替代实现的组合，并且每个配置满足完整集合集合处的目标到达时间窗口。 根据用于构造配置的数据（优选等待时间数据）的评估来选择配置。 不需要手动交互，并提供具有最小延迟的配置。