System of accessing data in a graphics system and method thereof
    1.
    发明授权
    System of accessing data in a graphics system and method thereof 有权
    在图形系统中访问数据的系统及其方法

    公开(公告)号:US06469703B1

    公开(公告)日:2002-10-22

    申请号:US09347202

    申请日:1999-07-02

    IPC分类号: G06F15167

    摘要: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the 10 controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.

    摘要翻译: 中央处理器单元(CPU)连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出(IO)控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常,IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外,10个控制器通过标准或专用总线协议与外部存储设备(如硬盘驱动器)进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中,两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。 因此,每个通道可以同时访问图形数据,同时访问系统数据,或同时访问图形和系统数据。 通过确保将物理地址划分为统一存储器内的块来实现同时访问,这样的数据块是相邻的块被不同的信道访问。

    Method and apparatus for accessing graphics cache memory
    2.
    发明授权
    Method and apparatus for accessing graphics cache memory 有权
    访问图形缓存的方法和装置

    公开(公告)号:US06173367B2

    公开(公告)日:2001-01-09

    申请号:US09314210

    申请日:1999-05-19

    IPC分类号: G06F1200

    摘要: A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.

    摘要翻译: 一种在具有2D和3D图形应用的系统中利用数据高速缓存的方法和装置。 在本发明的具体实施例中,视频系统接收模式信号,指示是否使用2D或3D应用。 根据模式信号,无论是作为能够被两个单独的数据访问流访问的统一高速缓存,还是两个独立的高速缓存,每个高速缓存由一个数据访问流访问。

    Memory device for providing data in a graphics system and method and apparatus therof
    3.
    发明授权
    Memory device for providing data in a graphics system and method and apparatus therof 有权
    用于在图形系统中提供数据的存储器件以及方法和装置

    公开(公告)号:US08924617B2

    公开(公告)日:2014-12-30

    申请号:US12429833

    申请日:2009-04-24

    摘要: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.

    摘要翻译: 中央处理器单元(CPU)连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出(IO)控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常,IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外,IO控制器通过标准或专用总线协议与外部存储设备(如硬盘驱动器)进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中,两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。

    Video controller for accessing data in a system and method thereof
    4.
    发明授权
    Video controller for accessing data in a system and method thereof 有权
    用于访问系统中的数据的视频控制器及其方法

    公开(公告)号:US06546449B1

    公开(公告)日:2003-04-08

    申请号:US09347201

    申请日:1999-07-02

    IPC分类号: G06F1336

    CPC分类号: G06F13/1684

    摘要: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.

    摘要翻译: 中央处理器单元(CPU)连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出(IO)控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常,IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外,IO控制器通过标准或专用总线协议与外部存储设备(如硬盘驱动器)进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中,两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。 因此,每个通道可以同时访问图形数据,同时访问系统数据,或同时访问图形和系统数据。 通过确保将物理地址划分为统一存储器内的块来实现同时访问,这样的数据块是相邻的块被不同的信道访问。

    System of accessing data in a graphics system and method thereof
    5.
    发明授权
    System of accessing data in a graphics system and method thereof 有权
    在图形系统中访问数据的系统及其方法

    公开(公告)号:US07543101B2

    公开(公告)日:2009-06-02

    申请号:US10075149

    申请日:2002-02-14

    IPC分类号: G06F13/36

    摘要: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.

    摘要翻译: 中央处理器单元(CPU)连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出(IO)控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常,IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外,IO控制器通过标准或专用总线协议与外部存储设备(如硬盘驱动器)进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中,两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。