公开(公告)号：US06633296B1

公开(公告)日：2003-10-14

申请号：US09579432

申请日：2000-05-26

申请人： Indra Laksono ,  Milivoje Aleksic ,  Antonio Asaro ,  Andrew E. Gruber ,  Gordon Caruk ,  Brian Lee

发明人： Indra Laksono ,  Milivoje Aleksic ,  Antonio Asaro ,  Andrew E. Gruber ,  Gordon Caruk ,  Brian Lee

IPC分类号： G06F1516

CPC分类号： G06F3/14 ,  G09G5/363 ,  G09G2352/00 ,  G09G2360/06

摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

摘要翻译： 在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换

公开(公告)号：US06546449B1

公开(公告)日：2003-04-08

申请号：US09347201

申请日：1999-07-02

申请人： Milivoje Aleksic ,  Raymond M. Li ,  Danny H. M. Cheng ,  Carl K. Mizuyabu ,  Antonio Asaro

发明人： Milivoje Aleksic ,  Raymond M. Li ,  Danny H. M. Cheng ,  Carl K. Mizuyabu ,  Antonio Asaro

IPC分类号： G06F1336

CPC分类号： G06F13/1684

摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.

摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。 因此，每个通道可以同时访问图形数据，同时访问系统数据，或同时访问图形和系统数据。 通过确保将物理地址划分为统一存储器内的块来实现同时访问，这样的数据块是相邻的块被不同的信道访问。

公开(公告)号：US6141024A

公开(公告)日：2000-10-31

申请号：US792784

申请日：1997-02-03

申请人： Indra Laksono ,  Antonio Asaro ,  Carl K. Mizuyabu

发明人： Indra Laksono ,  Antonio Asaro ,  Carl K. Mizuyabu

IPC分类号： G09G5/393 ,  G09G5/36

CPC分类号： G09G5/393

摘要： A rasterizer is used with a processor capable of providing raster data indicative of a pattern of pixels to be formed on a display. Each pixel has an attribute represented by a data value. The rasterizer has a replicator connected to form at least two copies of the raster data. A graphics engine is connected to use the at least two copies to store the data values in a memory. An output circuit is connected to use the data values stored in the memory to form the pattern on the display.

摘要翻译： 光栅化器与能够提供指示要在显示器上形成的像素的图案的光栅数据的处理器一起使用。 每个像素具有由数据值表示的属性。 光栅化器具有连接的复制器以形成光栅数据的至少两个副本。 连接图形引擎以使用至少两个副本将数据值存储在存储器中。 连接输出电路以使用存储在存储器中的数据值在显示器上形成图案。

公开(公告)号：US08219736B2

公开(公告)日：2012-07-10

申请号：US10074064

申请日：2002-02-12

申请人： Antonio Asaro ,  Brian Lee ,  Kuldip Sahdra ,  Gordon Caruk

发明人： Antonio Asaro ,  Brian Lee ,  Kuldip Sahdra ,  Gordon Caruk

IPC分类号： G06F13/36

CPC分类号： G06F3/14 ,  G06F13/404

摘要： A configurable register method and structure included configuration logic to form a register value. A data bridge system, for connecting an interface of a computer system to a plurality of application-specific integrated circuits (ASIC), has a data bridge operatively coupled between the computer interface and the plurality of ASICs that employs the configurable registers. The data bridge has a read only memory for storing at least the initial values and mask values for each ASIC of the plurality of ASICs. The data bridge upon initialization forms base address registers and other configuration data that are queried by the computer system. When the ASICs are graphic processors, the initial values and the mask values stored in the read only memory define the base address registers in the data bridge as a function of the configuration requirements of the graphic processors. The base address registers are thus programmable as a function of the initial values and mask values in the read only memory. The read only memory is coupled to the data bridge.

摘要翻译： 可配置的寄存器方法和结构包括用于形成寄存器值的配置逻辑。 用于将计算机系统的接口连接到多个专用集成电路（ASIC）的数据桥接系统具有可操作地耦合在计算机接口和采用可配置寄存器的多个ASIC之间的数据桥。 数据桥具有仅用于存储多个ASIC中的每个ASIC的至少初始值和掩码值的只读存储器。 初始化后的数据桥形成基本地址寄存器和计算机系统查询的其他配置数据。 当ASIC是图形处理器时，存储在只读存储器中的初始值和掩码值根据图形处理器的配置要求定义数据桥中的基地址寄存器。 因此，基址寄存器可以根据只读存储器中的初始值和掩码值进行编程。 只读存储器耦合到数据桥。

公开(公告)号：US20100281231A1

公开(公告)日：2010-11-04

申请号：US12431874

申请日：2009-04-29

申请人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

发明人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

IPC分类号： G06F12/00 ,  G06F9/46

CPC分类号： G06F13/161

摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

摘要翻译： 分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。 在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。 该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。 合并的非相干存储器请求流至少部分地基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

公开(公告)号：US06643756B1

公开(公告)日：2003-11-04

申请号：US09438308

申请日：1999-11-11

申请人： Milivoje Aleksic ,  Nader Akhlaghi-Tavasoli ,  Jason Chan ,  Carl Mizuyabu ,  Antonio Asaro

发明人： Milivoje Aleksic ,  Nader Akhlaghi-Tavasoli ,  Jason Chan ,  Carl Mizuyabu ,  Antonio Asaro

IPC分类号： G06F1200

CPC分类号： G06F3/14 ,  G06F12/1027 ,  G06F12/1081

摘要： A request for video or graphics data is made to a memory controller. When the memory controller determines a translation of the data must first be made, a request is made to a translator. The translator either translates the address or requests translation information from the memory controller. The memory controller accesses memory based upon the translator request. If the request is for translation data the results are tagged for the translator. If the translator request is for the translated address, the results are tagged for the original request.

摘要翻译： 对存储器控制器进行视频或图形数据的请求。 当存储器控制器确定首先需要进行数据的转换时，向翻译器发出请求。 翻译器翻译来自存储器控制器的地址或请求翻译信息。 存储器控制器根据翻译器请求访问存储器。 如果请求用于翻译数据，则结果将被标记为翻译器。 如果翻译请求是用于翻译的地址，结果将被标记为原始请求。

公开(公告)号：US06339427B1

公开(公告)日：2002-01-15

申请号：US09211637

申请日：1998-12-15

申请人： Indra Laksono ,  Antonio Asaro

发明人： Indra Laksono ,  Antonio Asaro

IPC分类号： G06T1500

CPC分类号： G06T15/005

摘要： A graphics display command list handler and method requests allocation of memory, such as system memory, in the form of a circular FIFO which stores the display command list as a memory display list (MDL), such as a host memory display list. A processor, such as a graphics processor, communicates a host memory display list read pointer to the host processor to facilitate display list signaling by the graphics processor. The host processor (or other processor) maintains a write pointer which points to a last host memory entry in the display list. The read pointer is maintained by the graphics processor and written back to the host processor.

摘要翻译： 图形显示命令列表处理程序和方法请求以循环FIFO的形式分配诸如系统存储器的存储显示命令列表作为诸如主机存储器显示列表的存储器显示列表（MDL）的存储器。 诸如图形处理器的处理器将主机存储器显示列表读取指针传送到主机处理器以便于图形处理器的显示列表信令。 主机处理器（或其他处理器）维护写入指针，该指针指向显示列表中的最后一个主机存储器条目。 读指针由图形处理器维护并写回到主处理器。

公开(公告)号：US6100906A

公开(公告)日：2000-08-08

申请号：US64569

申请日：1998-04-22

申请人： Antonio Asaro ,  Indra Laksono ,  James Doyle ,  Gordon F. Grigor

发明人： Antonio Asaro ,  Indra Laksono ,  James Doyle ,  Gordon F. Grigor

IPC分类号： G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G09G5/399 ,  G06F13/00

CPC分类号： G09G5/399 ,  G09G5/363

摘要： A method and apparatus for improved double buffering within a computing system begins when a series of data blocks are received from a central processing unit at a rate independent of a processing rate of a recipient engine. For example, a video graphics circuit receives a series of data blocks representing video frames from the central processing unit at a rate independent of the refresh rate of the display. As the data blocks are received, the video graphics circuit queues commands of the data blocks. Typically, the commands include processing commands and a processing rate synchronize command. To process the data blocks, the co-processor pulls commands from the queued list and processes them to produce recipient data. As the co-processor is producing the recipient data, it is utilizing a first buffer. The co-processor continues to process the commands and storing the results into the first buffer until the processing rate synchronize command is detected. At this point, the co-processor pauses processing of the commands. At the beginning of the next cycle of the processing rate, the recipient data is provided from the first buffer to the recipient engine and the co-processor resumes processing of commands, which relate to another data block. As the co-processor is processing the commands of the second data block, it is utilizing a second buffer to store the processed data, i.e., the second recipient data.

摘要翻译： 一种用于在计算系统内改进双缓冲的方法和装置开始于以与接收机发动机的处理速率无关的速率从中央处理单元接收一系列数据块时开始。 例如，视频图形电路以与显示器的刷新率无关的速率从中央处理单元接收表示视频帧的一系列数据块。 当数据块被接收时，视频图形电路对数据块的命令进行排队。 通常，命令包括处理命令和处理速率同步命令。 为了处理数据块，协处理器从排队列表中提取命令并处理它们以产生接收方数据。 当协处理器产生接收者数据时，它正在利用第一缓冲器。 协处理器继续处理命令并将结果存储到第一缓冲器中，直到检测到处理速率同步命令。 此时，协处理器暂停处理命令。 在处理速率的下一周期的开始，从第一缓冲器向接收者引擎提供接收者数据，并且协处理器恢复与另一个数据块有关的命令的处理。 当协处理器正在处理第二数据块的命令时，它利用第二缓冲器来存储经处理的数据，即第二接收者数据。

公开(公告)号：US20120331226A1

公开(公告)日：2012-12-27

申请号：US13600614

申请日：2012-08-31

申请人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

发明人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

IPC分类号： G06F12/08

CPC分类号： G06F13/161

摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

摘要翻译： 分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。 在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。 该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。 合并的非相干存储器请求流基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

公开(公告)号：US06728820B1

公开(公告)日：2004-04-27

申请号：US09579006

申请日：2000-05-26

申请人： Lee Brian ,  Indra Laksono ,  Antonio Asaro ,  Andrew E. Gruber ,  Gordon Caruk ,  Milivoje Aleksic

发明人： Lee Brian ,  Indra Laksono ,  Antonio Asaro ,  Andrew E. Gruber ,  Gordon Caruk ,  Milivoje Aleksic

IPC分类号： G06F1336

CPC分类号： G06F3/14

摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.

摘要翻译： 在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换。