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1.发明授权Memory device for providing data in a graphics system and method and apparatus therof 有权用于在图形系统中提供数据的存储器件以及方法和装置公开(公告)号：US08924617B2
公开(公告)日：2014-12-30
申请号：US12429833
申请日：2009-04-24
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。
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公开(公告)号：US07543101B2
公开(公告)日：2009-06-02
申请号：US10075149
申请日：2002-02-14
IPC分类号： G06F13/36
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。
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公开(公告)号：US06469703B1
公开(公告)日：2002-10-22
申请号：US09347202
申请日：1999-07-02
IPC分类号： G06F15167
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the 10 controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.
摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，10个控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。 因此，每个通道可以同时访问图形数据，同时访问系统数据，或同时访问图形和系统数据。 通过确保将物理地址划分为统一存储器内的块来实现同时访问，这样的数据块是相邻的块被不同的信道访问。
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公开(公告)号：US06546449B1
公开(公告)日：2003-04-08
申请号：US09347201
申请日：1999-07-02
IPC分类号： G06F1336
CPC分类号： G06F13/1684
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.
摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。 因此，每个通道可以同时访问图形数据，同时访问系统数据，或同时访问图形和系统数据。 通过确保将物理地址划分为统一存储器内的块来实现同时访问，这样的数据块是相邻的块被不同的信道访问。
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5.发明申请Memory Device for Providing Data in a Graphics System and Method and Apparatus Thereof 有权用于在图形系统中提供数据的存储器件及其方法和装置公开(公告)号：US20090307406A1
公开(公告)日：2009-12-10
申请号：US12429833
申请日：2009-04-24
IPC分类号： G06F13/36
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。
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6.发明授权公开(公告)号：US06486884B1
公开(公告)日：2002-11-26
申请号：US09314561
申请日：1999-05-19
IPC分类号： G06F1206
CPC分类号： H04N19/423
摘要： A method and apparatus for storing sequential data words associated with a block of data in a non-linear manner within the data block is taught such that any row or column associated with the data block may be accessed using a burst access. A row, or column of data accessed by a burst frees up instruction bandwidth of a video controller. In particular, it is assured that each row and column of data associated with the data block has at least one sequential pair of data words associated with it. By assuring at least one sequential pair of data words, it is possible to issue a burst request for a minimum of two words of data with each row access, or column access of the video controller.
摘要翻译： 教导以数据块中的非线性方式存储与数据块相关联的顺序数据字的方法和装置，使得可以使用突发存取来访问与数据块相关联的任何行或列。 由突发访问的一行或一列数据释放视频控制器的指令带宽。 特别地，确保与数据块相关联的每一行和数据列具有与其相关联的至少一个连续数据字对。 通过确保至少一个顺序的数据字对，可以对视频控制器的每一行访问或列访问发出至少两个数据字的突发请求。
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公开(公告)号：US06173367B2
公开(公告)日：2001-01-09
申请号：US09314210
申请日：1999-05-19
申请人： Milivoje Aleksic , James Yee , Danny H. M Cheng , John DeRoo , Andrew E. Gruber
发明人： Milivoje Aleksic , James Yee , Danny H. M Cheng , John DeRoo , Andrew E. Gruber
IPC分类号： G06F1200
CPC分类号： G06F12/0857 , G06F12/0848 , G06F12/0875
摘要： A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.
摘要翻译： 一种在具有2D和3D图形应用的系统中利用数据高速缓存的方法和装置。 在本发明的具体实施例中，视频系统接收模式信号，指示是否使用2D或3D应用。 根据模式信号，无论是作为能够被两个单独的数据访问流访问的统一高速缓存，还是两个独立的高速缓存，每个高速缓存由一个数据访问流访问。
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公开(公告)号：US08860851B2
公开(公告)日：2014-10-14
申请号：US13267677
申请日：2011-10-06
申请人： Sergiu R. Goma , Milivoje Aleksic
发明人： Sergiu R. Goma , Milivoje Aleksic
CPC分类号： H04N5/367
摘要： A technique for processing at least one bad pixel occurring in an image sensing system is provided. Dynamic bad pixel detection is performed on a plurality of streaming pixels taking from at least one controlled image and value and coordinate information for each bad pixel is subsequently stored as stored bad pixel information. Thereafter, static bad pixel correction may be performed based on the stored bad pixel information. The stored bad pixel information may be verified based on histogram analysis performed on the plurality of streaming pixels. The technique for processing bad pixels in accordance with the present invention may be embodied in suitable circuitry or, more broadly, within devices incorporating image sensing systems.
摘要翻译： 提供了用于处理在图像感测系统中出现的至少一个不良像素的技术。 对从至少一个受控图像获取的多个流像素执行动态坏像素检测，并且随后将每个坏像素的坐标信息存储为存储的不良像素信息。 此后，可以基于存储的不良像素信息来执行静态坏像素校正。 可以基于对多个流式像素执行的直方图分析来验证存储的不良像素信息。 根据本发明的用于处理不良像素的技术可以体现在合适的电路中，或者更广泛地体现在包括图像感测系统的设备内。
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公开(公告)号：US08667375B2
公开(公告)日：2014-03-04
申请号：US13367059
申请日：2012-02-06
申请人： Sergiu Goma , Milivoje Aleksic
发明人： Sergiu Goma , Milivoje Aleksic
IPC分类号： H03M13/03
CPC分类号： H04L1/0057 , H03M13/19 , H03M13/27 , H04L1/0083
摘要： To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.
摘要翻译： 为了导出用于管理数据错误的汉明码，为奇偶校验位选择一组至少四个奇偶校验位位置，这将保护一组数据位（其中每个数据位在数据位集合中具有数据位位置）。 确定每个数据位位置的综合征。 这涉及选择至少三个奇偶校验位位置的唯一子集。 唯一子集与至少一个其他唯一的至少三个奇偶校验位位置的子集共享至少一个奇偶校验位位置。 然后可以基于所确定的校正子针对每个奇偶校验位位置计算奇偶校验位值。 分组的报头可以被提供有定义分组的长度的单词和使用该单词生成的错误管理代码，从而可以检测单词中的错误并且可能被校正。
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10.发明申请SYSTEM AND METHOD FOR IMPROVING METHODS OF MANUFACTURING STEREOSCOPIC IMAGE SENSORS 有权用于改进制造立体图像传感器的方法的系统和方法公开(公告)号：US20130070055A1
公开(公告)日：2013-03-21
申请号：US13622318
申请日：2012-09-18
IPC分类号： H04N13/02
CPC分类号： H04N13/246
摘要： Described herein are methods, systems and apparatus to improve imaging sensor production yields. In one method, a stereoscopic image sensor pair is provided from a manufacturing line. One or more images of a correction pattern are captured by the image sensor pair. Correction angles of the sensor pair are determined based on the images of the correction pattern. The correction angles of the sensor pair are represented graphically in a three dimensional space. Analysis of the graphical representation of the correction angles through statistical processing results in a set of production correction parameters that may be input into a manufacturing line to improve sensor pair yields.
摘要翻译： 这里描述了改善成像传感器生产产量的方法，系统和装置。 在一种方法中，从生产线提供立体图像传感器对。 校正图案的一个或多个图像由图像传感器对捕获。 基于校正图案的图像来确定传感器对的校正角度。 传感器对的校正角在三维空间中以图形方式表示。 通过统计处理对校正角度的图形表示进行分析，得到一组生产校正参数，可以将其输入生产线以提高传感器对的产量。
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