-
公开(公告)号:US5784185A
公开(公告)日:1998-07-21
申请号:US699657
申请日:1996-08-19
IPC分类号: G02F1/015 , H04B10/50 , H04B10/508 , H04J20060101 , H04J3/00 , H04J3/02 , H04J3/04 , H04J14/08 , H04L7/00 , H04L7/033
CPC分类号: H04B10/505 , H04B10/508 , H04J14/08 , H04L7/0037 , H04L7/0075 , H04J14/083 , H04L7/0337
摘要: A receiver at a node in an optical network receives an optical clock signal and an OTDM datastream. A detector converts the clock signal to the electrical domain. A variable delay stage applies a selected delay to the clock signal in the electrical domain. A non-linear electro-optic modulator which may be an electro-absorption modulator, receives the OTDM datastream at its optical input. An electrical control input of the modulator is connected to the output of the variable delay stage. The electro-optic modulator outputs an OTDM channel selected by setting the delay of the variable delay stage. The variable delay stage may include a number of logic gates, particularly AND gates, connected between a pair of microstrip delay lines. The gates are controlled to provide different paths with different corresponding delay times for the clock signal.
摘要翻译: 光网络中的节点处的接收机接收光时钟信号和OTDM数据流。 检测器将时钟信号转换为电域。 可变延迟级将选择的延迟施加到电域中的时钟信号。 可以是电吸收调制器的非线性电光调制器在其光输入处接收OTDM数据流。 调制器的电气控制输入连接到可变延迟级的输出端。 电光调制器通过设置可变延迟级的延迟来输出选择的OTDM信道。 可变延迟级可以包括连接在一对微带延迟线之间的多个逻辑门,特别是与门。 门被控制以为时钟信号提供具有不同相应延迟时间的不同路径。