公开(公告)号：US07408394B2

公开(公告)日：2008-08-05

申请号：US11900451

申请日：2007-09-11

申请人： David A. Zimlich

发明人： David A. Zimlich

IPC分类号： H03H11/26

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03K5/135

摘要： A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.

摘要翻译： 测量控制延迟包括测量延迟线和信号产生延迟线，每个延迟线包括多个串联连接的延迟单元。 数字信号被施加到测量延迟线中的初始延迟单元，并且它依次传播通过延迟单元，直到接收到第二数字信号。 这些输出被施加到信号产生延迟线的控制输入，以控制时钟信号在从最终延迟单元输出之前传播的延迟单元的数量。 测量延迟线中的每个延迟单元包括一对串联的或非门。 最初施加数字信号的或非门作为触发器耦合到第二或非门，使得在将数字信号施加到测量延迟线之后，或非门的输出保持恒定。

公开(公告)号：US06451513B1

公开(公告)日：2002-09-17

申请号：US09568560

申请日：2000-05-09

申请人： David A. Zimlich ,  David H. Wells

发明人： David A. Zimlich ,  David H. Wells

IPC分类号： G03C500

CPC分类号： G03F1/34

摘要： A phase-shifting lithographic mask, a method for its fabrication, and a method for its use in forming field-emission display emitters is described. The mask is made from a plate and has field and pattern regions that both transmit light of a given wavelength. The pattern region is a plurality of regularly spaced etched regions of the plate, with the optical path length of the pattern region differing from the optical path length of the field region by an odd integer multiple of one-half the light wavelength. Use of phase-shifting lithography improves depth-of-focus, and correspondingly relaxes planarity requirements. The pattern region of the mask is sized to expose a photoresist layer used in fabricating field-emission display emitters in just a single light exposure, thereby avoiding the disadvantages associated with conventional dual pass phase-shifting lithography.

公开(公告)号：US06201977B1

公开(公告)日：2001-03-13

申请号：US09066616

申请日：1998-04-24

申请人： David A. Cathey ,  Kip A. Bedard ,  David A. Zimlich

发明人： David A. Cathey ,  Kip A. Bedard ,  David A. Zimlich

IPC分类号： H04M100

CPC分类号： H04W88/02 ,  H02J7/0063 ,  H02J2007/0067 ,  H04B1/3805 ,  H04W52/0277 ,  Y02D70/40

摘要： Method and apparatus for ensuring that, in a portable, battery-powered communication package incorporating at least two communication devices, such as a combination cellular telephone and a pager, sufficient power is provided for extended operation of the communication device having the lowest continuous power consumption requirements when the device having a higher continuous power consumption rate has consumed a selected portion of the total power initially available to the combined devices. In the case of the aforestated exemplary device, cellular telephone function is disabled when a selected portion of the total power initially available is consumed. A first embodiment of the invention is implemented with a single electrochemical battery. The first embodiment of the invention may include a headroom-limited flyback power supply which powers the high-power consumption device. When headroom drops below a minimum set by a series-coupled diode string, power is cut off to the high-power-consumption device. The first embodiment of the invention may alternatively include a battery charge sense circuit which produces a digital signal, the digital signal corresponding to either a battery charge state that is above the predetermined voltage level or a battery charge state that is below the predetermined voltage level. For this alternate first embodiment, operation of the high-power-consumption device is disabled when the predetermined battery charge state is reached, thus permitting operation of the low-power consumption communication device for an extended period which, ideally, should be at least 24 hours. A second embodiment of the invention is implemented using a separate electrochemical power source (e.g., a single electrochemical cell or battery) to power the low-power consumption device.

摘要翻译： 提供一种用于确保在具有至少两个通信设备（诸如组合蜂窝电话和寻呼机）的便携式电池供电通信包中提供足够的功率以用于具有最低连续功耗的通信设备的扩展操作的方法和装置 当具有较高连续功率消耗率的设备已经消耗了组合设备最初可用的总功率的选定部分时的要求。 在上述示例性设备的情况下，当消耗最初可用的总功率的所选部分时，禁用蜂窝电话功能。 本发明的第一实施例用单个电化学电池实现。 本发明的第一实施例可以包括为大功率消耗装置供电的净空限制回扫电源。 当余量低于由串联二极管串设置的最小值时，电源将切断到高功耗器件。 本发明的第一实施例可以替代地包括产生数字信号的电池电荷感测电路，对应于高于预定电压电平的电池充电状态或低于预定电压电平的电池充电状态的数字信号。 对于该替代的第一实施例，当达到预定电池充电状态时，高功率消耗装置的操作被禁用，从而允许低功耗通信装置的操作延长的时间段，理想地应当是至少24 小时。 使用单独的电化学电源（例如，单个电化学电池或电池）来实现本发明的第二实施例以为低功率消耗装置供电。

公开(公告)号：US06169371A

公开(公告)日：2001-01-02

申请号：US09496561

申请日：2000-02-02

申请人： David A. Zimlich ,  David A. Cathey, Jr.

发明人： David A. Zimlich ,  David A. Cathey, Jr.

IPC分类号： G09G310

CPC分类号： G09G3/22 ,  G09G2300/08 ,  G09G2310/0289 ,  G09G2330/026 ,  H01J3/022 ,  H01J29/98 ,  H01J2329/00

摘要： A field emission display includes an array of emitter sites, a grid for controlling electron emission from the emitter sites, and a display screen. The field emission display also includes a control circuit for controlling the grid for preventing emission to grid. The control circuit includes a high impedance grid bias path, and a low impedance grid bias path. In addition, the control circuit includes a sensing-switching circuit for sensing an anode voltage at the display screen, and switching from the high impedance to the low impedance grid bias path upon detection of a threshold anode voltage. An alternate embodiment control circuit is configured to provide a programmable delay during enabling of the grid to insure that the display screen reaches the threshold voltage prior to electron emission. An alternate embodiment field emission display includes a focus ring that is controlled to prevent emission to grid.

摘要翻译： 场发射显示器包括发射极阵列阵列，用于控制从发射器位置发射电子的栅格和显示屏。 场发射显示器还包括用于控制电网以防止发射到电网的控制电路。 控制电路包括高阻抗栅极偏置路径和低阻抗栅极偏置路径。 此外，控制电路包括用于感测显示屏幕上的阳极电压的感测切换电路，以及在检测到阈值阳极电压时从高阻抗切换到低阻抗栅极偏置路径。 替代实施例控制电路被配置为在网格启用期间提供可编程延迟，以确保显示屏在电子发射之前达到阈值电压。 替代实施例的场致发射显示器包括被控制以防止发射到电网的聚焦环。

公开(公告)号：US06735456B2

公开(公告)日：2004-05-11

申请号：US10307140

申请日：2002-11-27

申请人： David A. Cathey ,  Kip A. Bedard ,  David A. Zimlich

发明人： David A. Cathey ,  Kip A. Bedard ,  David A. Zimlich

IPC分类号： H04M100

CPC分类号： H04W88/02 ,  H02J7/0063 ,  H02J2007/0067 ,  H04B1/3805 ,  H04W52/0277 ,  Y02D70/40

摘要： Apparatus for ensuring that, in a portable, battery-powered communication package incorporating at least two communication devices, such as a combination cellular telephone and a pager, sufficient power is provided for extended operation of the communication device having the lowest continuous power consumption requirements when the device having a higher continuous power consumption rate has consumed a selected portion of the total power initially available to the combined devices.

摘要翻译： 用于确保在携带电池供电的通信包中包含诸如组合蜂窝电话和寻呼机的至少两个通信设备的足够功率的设备用于具有最低连续功耗要求的通信设备的扩展操作， 具有较高连续功率消耗率的设备消耗了组合设备最初可用的总功率的选定部分。

公开(公告)号：US06534244B1

公开(公告)日：2003-03-18

申请号：US09718580

申请日：2000-11-21

申请人： David A. Zimlich ,  David H. Wells

发明人： David A. Zimlich ,  David H. Wells

IPC分类号： G03C500

CPC分类号： G03F1/34

摘要： A phase-shifting lithographic mask, a method for its fabrication, and a method for its use in forming field-emission display emitters is described. The mask is made from a plate and has field and pattern regions that both transmit light of a given wavelength. The pattern region is a plurality of regularly spaced etched regions of the plate, with the optical path length of the pattern region differing from the optical path length of the field region by an odd integer multiple of one-half the light wavelength. Use of phase-shifting lithography improves depth-of-focus, and correspondingly relaxes planarity requirements. The pattern region of the mask is sized to expose a photoresist layer used in fabricating field-emission display emitters in just a single light exposure, thereby avoiding the disadvantages associated with conventional dual pass phase-shifting lithography.

公开(公告)号：US06461774B1

公开(公告)日：2002-10-08

申请号：US09141841

申请日：1998-08-27

申请人： David A. Zimlich ,  David H. Wells

发明人： David A. Zimlich ,  David H. Wells

IPC分类号： G03F900

CPC分类号： G03F1/34

摘要： A phase-shifting lithographic mask, a method for its fabrication, and a method for its use in forming field-emission display emitters is described. The mask is made from a plate and has field and pattern regions that both transmit light of a given wavelength. The pattern region is a plurality of regularly spaced etched regions of the plate, with the optical path length of the pattern region differing from the optical path length of the field region by an odd integer multiple of one-half the light wavelength. Use of phase-shifting lithography improves depth-of-focus, and correspondingly relaxes planarity requirements. The pattern region of the mask is sized to expose a photoresist layer used in fabricating field-emission display emitters in just a single light exposure, thereby avoiding the disadvantages associated with conventional dual pass phase-shifting lithography.

摘要翻译： 描述了相移光刻掩模，其制造方法及其在形成场致发射显示发射体中的用途。 掩模由板制成，并且具有透射给定波长的光的场和图案区域。 图案区域是板的多个规则间隔的蚀刻区域，图案区域的光程长度不同于场区域的光程长度为光波长一半的奇整数倍。 使用相移光刻技术可提高焦点深度，并相应地松弛平面度要求。 掩模的图案区域的尺寸设定为仅在单个曝光中曝光制造场致发射显示器发射器中所用的光致抗蚀剂层，从而避免了与常规双路相移光刻相关的缺点。

公开(公告)号：US07688129B2

公开(公告)日：2010-03-30

申请号：US11881335

申请日：2007-07-25

申请人： David A. Zimlich

发明人： David A. Zimlich

IPC分类号： H03K3/00

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/4076 ,  H03H11/26

摘要： Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series of feedback delay circuits mirror respective first delay circuits. After the input signal has been coupled through the first delay circuits, the mirrored signals from the first delay circuits are coupled through the feedback delay circuits. The delay of the feedback delay circuits is one-half the delay of the first delay circuits to provide a signal that is the quadrature of the clock signal.

摘要翻译： 以类似于同步镜延迟电路的方式使用延迟电路，以从输入时钟信号产生正交时钟信号。 输入时钟信号通过一系列第一延迟电路耦合输入时钟信号的一半周期。 第二系列反馈延迟电路镜像各自的第一延迟电路。 在通过第一延迟电路耦合输入信号之后，来自第一延迟电路的镜像信号通过反馈延迟电路耦合。 反馈延迟电路的延迟是第一延迟电路的延迟的一半，以提供作为时钟信号的正交的信号。

公开(公告)号：US07274237B2

公开(公告)日：2007-09-25

申请号：US11219302

申请日：2005-09-01

申请人： David A. Zimlich

发明人： David A. Zimlich

IPC分类号： H03H11/26

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03K5/135

摘要： A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.

摘要翻译： 测量控制延迟包括测量延迟线和信号产生延迟线，每个延迟线包括多个串联连接的延迟单元。 数字信号被施加到测量延迟线中的初始延迟单元，并且它依次传播通过延迟单元，直到接收到第二数字信号。 这些输出被施加到信号产生延迟线的控制输入，以控制时钟信号在从最终延迟单元输出之前传播的延迟单元的数量。 测量延迟线中的每个延迟单元包括一对串联的或非门。 最初施加数字信号的或非门作为触发器耦合到第二或非门，使得在将数字信号施加到测量延迟线之后，或非门的输出保持恒定。

公开(公告)号：US07084686B2

公开(公告)日：2006-08-01

申请号：US10854849

申请日：2004-05-25

申请人： David A. Zimlich

发明人： David A. Zimlich

IPC分类号： G06F1/04

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C11/4076 ,  H03H11/26

摘要： Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input clock signal is coupled through a series of first delay circuit for one-half the period of the input clock signal. A second series of feedback delay circuits mirror respective first delay circuits. After the input signal has been coupled through the first delay circuits, the mirrored signals from the first delay circuits are coupled through the feedback delay circuits. The delay of the feedback delay circuits is one-half the delay of the first delay circuits to provide a signal that is the quadrature of the clock signal.

摘要翻译： 以类似于同步镜延迟电路的方式使用延迟电路，以从输入时钟信号产生正交时钟信号。 输入时钟信号通过一系列第一延迟电路耦合输入时钟信号的一半周期。 第二系列反馈延迟电路镜像各自的第一延迟电路。 在通过第一延迟电路耦合输入信号之后，来自第一延迟电路的镜像信号通过反馈延迟电路耦合。 反馈延迟电路的延迟是第一延迟电路的延迟的一半，以提供作为时钟信号的正交的信号。