公开(公告)号：US06451513B1

公开(公告)日：2002-09-17

申请号：US09568560

申请日：2000-05-09

申请人： David A. Zimlich ,  David H. Wells

发明人： David A. Zimlich ,  David H. Wells

IPC分类号： G03C500

CPC分类号： G03F1/34

摘要： A phase-shifting lithographic mask, a method for its fabrication, and a method for its use in forming field-emission display emitters is described. The mask is made from a plate and has field and pattern regions that both transmit light of a given wavelength. The pattern region is a plurality of regularly spaced etched regions of the plate, with the optical path length of the pattern region differing from the optical path length of the field region by an odd integer multiple of one-half the light wavelength. Use of phase-shifting lithography improves depth-of-focus, and correspondingly relaxes planarity requirements. The pattern region of the mask is sized to expose a photoresist layer used in fabricating field-emission display emitters in just a single light exposure, thereby avoiding the disadvantages associated with conventional dual pass phase-shifting lithography.

公开(公告)号：US06534244B1

公开(公告)日：2003-03-18

申请号：US09718580

申请日：2000-11-21

申请人： David A. Zimlich ,  David H. Wells

发明人： David A. Zimlich ,  David H. Wells

IPC分类号： G03C500

CPC分类号： G03F1/34

摘要： A phase-shifting lithographic mask, a method for its fabrication, and a method for its use in forming field-emission display emitters is described. The mask is made from a plate and has field and pattern regions that both transmit light of a given wavelength. The pattern region is a plurality of regularly spaced etched regions of the plate, with the optical path length of the pattern region differing from the optical path length of the field region by an odd integer multiple of one-half the light wavelength. Use of phase-shifting lithography improves depth-of-focus, and correspondingly relaxes planarity requirements. The pattern region of the mask is sized to expose a photoresist layer used in fabricating field-emission display emitters in just a single light exposure, thereby avoiding the disadvantages associated with conventional dual pass phase-shifting lithography.

公开(公告)号：US06461774B1

公开(公告)日：2002-10-08

申请号：US09141841

申请日：1998-08-27

申请人： David A. Zimlich ,  David H. Wells

发明人： David A. Zimlich ,  David H. Wells

IPC分类号： G03F900

CPC分类号： G03F1/34

摘要： A phase-shifting lithographic mask, a method for its fabrication, and a method for its use in forming field-emission display emitters is described. The mask is made from a plate and has field and pattern regions that both transmit light of a given wavelength. The pattern region is a plurality of regularly spaced etched regions of the plate, with the optical path length of the pattern region differing from the optical path length of the field region by an odd integer multiple of one-half the light wavelength. Use of phase-shifting lithography improves depth-of-focus, and correspondingly relaxes planarity requirements. The pattern region of the mask is sized to expose a photoresist layer used in fabricating field-emission display emitters in just a single light exposure, thereby avoiding the disadvantages associated with conventional dual pass phase-shifting lithography.

摘要翻译： 描述了相移光刻掩模，其制造方法及其在形成场致发射显示发射体中的用途。 掩模由板制成，并且具有透射给定波长的光的场和图案区域。 图案区域是板的多个规则间隔的蚀刻区域，图案区域的光程长度不同于场区域的光程长度为光波长一半的奇整数倍。 使用相移光刻技术可提高焦点深度，并相应地松弛平面度要求。 掩模的图案区域的尺寸设定为仅在单个曝光中曝光制造场致发射显示器发射器中所用的光致抗蚀剂层，从而避免了与常规双路相移光刻相关的缺点。

公开(公告)号：US08791447B2

公开(公告)日：2014-07-29

申请号：US13010048

申请日：2011-01-20

申请人： Zengtao T. Liu ,  David H. Wells

发明人： Zengtao T. Liu ,  David H. Wells

IPC分类号： H01L29/06

CPC分类号： H01L27/2409 ,  G11C5/02 ,  H01L27/249 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

摘要： A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and second electrodes. Current conductive material is in series between and with the programmable material and the select device. An array of vertically stacked tiers of such nonvolatile memory cells is disclosed. Methods of forming arrays of nonvolatile memory cells are disclosed.

摘要翻译： 非易失性存储单元包括第一和第二电极。 可编程材料和选择装置被串联接纳在第一和第二电极之间。 当前导电材料与可编程材料和选择装置之间串联在一起。 公开了这种非易失性存储单元的垂直层叠的阵列。 公开了形成非易失性存储单元阵列的方法。

公开(公告)号：US20130069030A1

公开(公告)日：2013-03-21

申请号：US13234875

申请日：2011-09-16

申请人： David H. Wells ,  D.V. Nirmal Ramaswamy ,  Kirk D. Prall

发明人： David H. Wells ,  D.V. Nirmal Ramaswamy ,  Kirk D. Prall

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L45/085 ,  G11C2213/73 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146

摘要： Resistive memory cells including an integrated select device and storage element and methods of forming the same are described herein. As an example, a resistive memory cell can include a select device structure including a Schottky interface, and a storage element integrated with the select device structure such that an electrode corresponding to the Schottky interface serves as a first electrode of the storage element. The storage element can include a storage material formed between the first electrode and a second electrode.

摘要翻译： 包括集成选择装置和存储元件的电阻式存储单元及其形成方法在此描述。 作为示例，电阻式存储单元可以包括包括肖特基接口的选择器件结构和与选择器件结构集成的存储元件，使得对应于肖特基界面的电极用作存储元件的第一电极。 存储元件可以包括形成在第一电极和第二电极之间的存储材料。

公开(公告)号：US08283198B2

公开(公告)日：2012-10-09

申请号：US12776764

申请日：2010-05-10

申请人： David H. Wells

发明人： David H. Wells

IPC分类号： H01L21/00 ,  H01L29/08

CPC分类号： H01L45/126 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144 ,  H01L45/16

摘要： Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material.

摘要翻译： 本文描述了电阻存储器和处理电阻性存储器的方法。 处理电阻性存储器的一个或多个方法实施例包括在具有存取装置接触的电极上形成电阻性存储单元材料，以及在电阻上形成电阻式存储单元材料之后，在电阻式存储单元材料上形成加热器电极，使得加热器 电极与电阻式存储单元材料自对准。

公开(公告)号：US20120182787A1

公开(公告)日：2012-07-19

申请号：US13430970

申请日：2012-03-27

申请人： David H. Wells ,  Jun Liu

发明人： David H. Wells ,  Jun Liu

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C5/02 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0054

摘要： Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

摘要翻译： 存储器件包括多个存储器单元，每个存储器单元包括存储元件和选择器件。 多个第一（例如，行）地址线可以在多个的至少一些单元的第一侧相邻（例如，在下方）。 多个第二（例如，列）地址线跨越多个行地址线延伸，每个列地址线在至少一些单元的第二相对侧相邻（例如，在上）。 控制电路可以被配置为基本上同时向地址线施加读取电压或写入电压。 还公开了包括这种存储器件的系统和至少基本上同时访问多个单元的方法。

公开(公告)号：US20100308438A1

公开(公告)日：2010-12-09

申请号：US12477551

申请日：2009-06-03

申请人： David H. Wells

发明人： David H. Wells

IPC分类号： H01L21/027 ,  H01L23/58

CPC分类号： H01L21/3083 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76224

摘要： A method for fabricating semiconductor device structures includes forming a non-conformal mask over a surface of a substrate. Non-conformal mask material with a planar or substantially planar upper surface is formed on the surface of the substrate. The planarity or substantial planarity of the non-conformal material eliminates or substantially eliminates distortion in a “mask” formed thereover and, thus, eliminates or substantially eliminates distortion in any mask that is subsequently formed using the pattern of the mask. In some embodiments, mask material of the non-conformal mask does not extend into recesses in the upper surface of the substrate; instead it “bridges” the recesses. Semiconductor device structures that include non-conformal masks and semiconductor device structures that have been fabricated with non-conformal masks are also disclosed.

摘要翻译： 一种制造半导体器件结构的方法包括在衬底的表面上形成非共形掩模。 在基板的表面上形成具有平面或基本平坦的上表面的非保形掩模材料。 非保形材料的平面度或实质平面度消除或基本上消除了在其上形成的“掩模”中的失真，并因此消除或基本上消除随后使用掩模图案形成的任何掩模中的畸变。 在一些实施例中，非保形掩模的掩模材料不延伸到衬底的上表面中的凹槽中; 而是“桥”了凹槽。 还公开了包括使用非保形掩模制造的非共形掩模和半导体器件结构的半导体器件结构。

公开(公告)号：US20100276741A1

公开(公告)日：2010-11-04

申请号：US12836404

申请日：2010-07-14

申请人： David H. Wells

发明人： David H. Wells

IPC分类号： H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10808 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.

摘要翻译： 公开了一种形成掩埋数字线的方法。 牺牲隔离物沿着隔离沟槽的侧壁形成，然后用牺牲材料填充。 一个间隔物被屏蔽，而另一个间隔物被去除，并且在去除的间隔物下方的衬底中的蚀刻步骤形成隔离窗。 然后，绝缘衬垫沿着排空的沟槽的侧壁形成，包括进入隔离窗。 然后在绝缘衬垫之间通过沟槽的底部形成数字线凹槽，这两个绝缘衬垫作为掩模加倍以自对准该蚀刻。 然后，数字线凹槽填充有金属和凹进的后部，并且具有可选的预先绝缘元件，并且沉积在凹部的底部中。

公开(公告)号：US20100171176A1

公开(公告)日：2010-07-08

申请号：US12725797

申请日：2010-03-17

申请人： David H. Wells

发明人： David H. Wells

IPC分类号： H01L23/34 ,  H01L29/786 ,  H01L21/336

CPC分类号： H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

摘要： Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

摘要翻译： 一些实施例包括在半导体结构内形成空隙的方法。 在一些实施例中，空隙可以用作用于分配冷却剂的微结构，用于引导电磁辐射，或用于材料的分离和/或表征。 一些实施例包括其中具有对应于空隙，导管，绝缘结构，半导体结构或导电结构的微结构的结构。