利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.022 秒)

    Method of making amorphous silicon on insulator VLSI circuit structures with floating gates
    9.
    发明授权
    Method of making amorphous silicon on insulator VLSI circuit structures with floating gates 失效
    制造具有浮动栅极的绝缘体上的非晶硅VLSI电路结构的方法

    公开(公告)号：US6017794A

    公开(公告)日：2000-01-25

    申请号：US974782

    申请日：1997-11-20

    申请人： Stanley G. Burns ,  Carl Gruber ,  Howard R. Shanks ,  Alan P. Constant ,  Allen R. Landin ,  David H. Schmidt

    发明人： Stanley G. Burns ,  Carl Gruber ,  Howard R. Shanks ,  Alan P. Constant ,  Allen R. Landin ,  David H. Schmidt

    IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L21/8247

    CPC分类号： H01L29/78696 ,  H01L21/84 ,  H01L27/1214 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78669 ,  H01L29/7881 ,  H01L29/7883

    摘要： An integrated thin film transistor on insulator circuit made up of a number of thin film transistors formed with small feature size and densely packed so as to allow interconnection as a complex circuit. An insulating substrate, preferably flexible, serves as the support layer for the integrated circuit. Control gate metallization is carried on the insulating substrate, a dielectric layer is deposited over the control gate, and an amorphous silicon layer with doped source and drain regions deposited on the dielectric layer. Trenches are formed to remove the amorphous silicon material between transistors to allow highly dense circuit packing. An upper interconnect level which forms connections to the source and drain and gate regions of the thin film transistors, also interconnects the transistors to form more complex circuit structures. Due to the dense packing of the transistors allowed by the trench isolation, the interconnecting foils can be relatively short, increasing the speed of the circuit.

    摘要翻译： 一种绝缘体上集成薄膜晶体管，由多个形成有小尺寸并且密集封装的薄膜晶体管构成，以便允许作为复杂电路的互连。 优选地，柔性的绝缘衬底用作集成电路的支撑层。 控制栅极金属化承载在绝缘基板上，介电层沉积在控制栅极上，并且具有沉积在介电层上的掺杂源极和漏极区域的非晶硅层。 形成沟槽以去除晶体管之间的非晶硅材料，以允许高度密集的电路封装。 形成与薄膜晶体管的源极和漏极和栅极区域的连接的上部互连电平，还互连晶体管以形成更复杂的电路结构。 由于沟道隔离允许的晶体管的密集封装，互连箔可以相对较短，从而增加了电路的速度。