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12 条记录 (耗时 0.033 秒)

    Amorphous silicon on insulator VLSI circuit structures
    1.
    发明授权
    Amorphous silicon on insulator VLSI circuit structures 失效
    非晶硅绝缘体VLSI电路结构

    公开(公告)号：US5742075A

    公开(公告)日：1998-04-21

    申请号：US751785

    申请日：1996-11-18

    申请人： Stanley G. Burns ,  Carl Gruber ,  Howard R. Shanks ,  Alan P. Constant ,  Allen R. Landin ,  David H. Schmidt

    发明人： Stanley G. Burns ,  Carl Gruber ,  Howard R. Shanks ,  Alan P. Constant ,  Allen R. Landin ,  David H. Schmidt

    IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L29/04

    CPC分类号： H01L29/78696 ,  H01L21/84 ,  H01L27/1214 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78669 ,  H01L29/7881 ,  H01L29/7883

    摘要： An integrated thin film transistor on insulator circuit made up of a number of thin film transistors formed with small feature size and densely packed so as to allow interconnection as a complex circuit. An insulating substrate, preferably flexible, serves as the support layer for the integrated circuit. Control gate metallization is carried on the insulating substrate, a dielectric layer is deposited over the control gate, and an amorphous silicon layer with doped source and drain regions deposited on the dielectric layer. Trenches are formed to remove the amorphous silicon material between transistors to allow highly dense circuit packing. An upper interconnect level which forms connections to the source and drain and gate regions of the thin film transistors, also interconnects the transistors to form more complex circuit structures. Due to the dense packing of the transistors allowed by the trench isolation, the interconnecting foils can be relatively short, increasing the speed of the circuit.

    摘要翻译： 一种绝缘体上集成薄膜晶体管，由多个形成有小尺寸并且密集封装的薄膜晶体管构成，以便允许作为复杂电路的互连。 优选地，柔性的绝缘衬底用作集成电路的支撑层。 控制栅极金属化承载在绝缘基板上，介电层沉积在控制栅极上，并且具有沉积在介电层上的掺杂源极和漏极区域的非晶硅层。 形成沟槽以去除晶体管之间的非晶硅材料，以允许高度密集的电路封装。 形成与薄膜晶体管的源极和漏极和栅极区域的连接的上部互连电平，还互连晶体管以形成更复杂的电路结构。 由于沟道隔离允许的晶体管的密集封装，互连箔可以相对较短，从而增加了电路的速度。

    Method of making amorphous silicon on insulator VLSI circuit structures with floating gates
    2.
    发明授权
    Method of making amorphous silicon on insulator VLSI circuit structures with floating gates 失效
    制造具有浮动栅极的绝缘体上的非晶硅VLSI电路结构的方法

    公开(公告)号：US6017794A

    公开(公告)日：2000-01-25

    申请号：US974782

    申请日：1997-11-20

    申请人： Stanley G. Burns ,  Carl Gruber ,  Howard R. Shanks ,  Alan P. Constant ,  Allen R. Landin ,  David H. Schmidt

    发明人： Stanley G. Burns ,  Carl Gruber ,  Howard R. Shanks ,  Alan P. Constant ,  Allen R. Landin ,  David H. Schmidt

    IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L21/8247

    CPC分类号： H01L29/78696 ,  H01L21/84 ,  H01L27/1214 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78669 ,  H01L29/7881 ,  H01L29/7883

    摘要： An integrated thin film transistor on insulator circuit made up of a number of thin film transistors formed with small feature size and densely packed so as to allow interconnection as a complex circuit. An insulating substrate, preferably flexible, serves as the support layer for the integrated circuit. Control gate metallization is carried on the insulating substrate, a dielectric layer is deposited over the control gate, and an amorphous silicon layer with doped source and drain regions deposited on the dielectric layer. Trenches are formed to remove the amorphous silicon material between transistors to allow highly dense circuit packing. An upper interconnect level which forms connections to the source and drain and gate regions of the thin film transistors, also interconnects the transistors to form more complex circuit structures. Due to the dense packing of the transistors allowed by the trench isolation, the interconnecting foils can be relatively short, increasing the speed of the circuit.

    摘要翻译： 一种绝缘体上集成薄膜晶体管，由多个形成有小尺寸并且密集封装的薄膜晶体管构成，以便允许作为复杂电路的互连。 优选地，柔性的绝缘衬底用作集成电路的支撑层。 控制栅极金属化承载在绝缘基板上，介电层沉积在控制栅极上，并且具有沉积在介电层上的掺杂源极和漏极区域的非晶硅层。 形成沟槽以去除晶体管之间的非晶硅材料，以允许高度密集的电路封装。 形成与薄膜晶体管的源极和漏极和栅极区域的连接的上部互连电平，还互连晶体管以形成更复杂的电路结构。 由于沟道隔离允许的晶体管的密集封装，互连箔可以相对较短，从而增加了电路的速度。

    Dielectric for amorphous silicon transistors
    3.
    发明授权
    Dielectric for amorphous silicon transistors 失效
    非晶硅晶体管的介质

    公开(公告)号：US5856690A

    公开(公告)日：1999-01-05

    申请号：US763550

    申请日：1996-12-10

    申请人： Stanley G. Burns ,  Carl Gruber ,  Howard R. Shanks ,  Allan P. Constant ,  Allen R. Landin ,  David H. Schmidt

    发明人： Stanley G. Burns ,  Carl Gruber ,  Howard R. Shanks ,  Allan P. Constant ,  Allen R. Landin ,  David H. Schmidt

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/788

    CPC分类号： H01L29/66825 ,  H01L21/28158 ,  H01L29/4908 ,  H01L29/511 ,  H01L29/7881

    摘要： A thin film floating gate transistor with improved dielectric structure. The dielectric structure serves the purpose of encapsulating the floating gate and also interfacing with the semiconductor material, .alpha.-Si:H. It thus must meet a variety of requirements. In order to provide long memory retention times, the dielectric material, at least in the regions encapsulating the floating gate, must have a high resistivity, on the order of 10.sup.17 ohm-cm or better. Silicon dioxide is the preferred material for encapsulating the floating gate. However, since silicon dioxide creates a high density of defect state when interfaced with the .alpha.-Si:H layer. An interface layer, substantially free of oxide, is interposed between the high resistivity layer and the .alpha.-Si:H. Preferably, the interface portion of the dielectric layer is silicon nitride. In some cases, it is desirable to replace the entire dielectric structure, or at least the interface layer with aluminum nitride.

    摘要翻译： 具有改善电介质结构的薄膜浮栅晶体管。 电介质结构用于封装浮动栅极并且还与半导体材料α-Si：H接合。 因此必须满足各种要求。 为了提供长的记忆保留时间，介电材料至少在封装浮动栅极的区域中必须具有大约1017欧姆 - 厘米或更高的高电阻率。 二氧化硅是用于封装浮动栅极的优选材料。 然而，由于当与α-Si层形成界面时，二氧化硅产生高密度缺陷状态。 基本上不含氧化物的界面层介于高电阻率层和α-Si：H之间。 优选地，电介质层的界面部分是氮化硅。 在一些情况下，期望用氮化铝代替整个电介质结构，或至少替代界面层。