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    Method of mapping multiple address spaces into single PCI bus
    4.
    发明授权
    Method of mapping multiple address spaces into single PCI bus 失效
    将多个地址空间映射到单个PCI总线的方法

    公开(公告)号：US06721839B1

    公开(公告)日：2004-04-13

    申请号：US09748983

    申请日：2000-12-27

    申请人： Ellen Marie Bauman ,  David Lee Dosch ,  Charles Scott Graham ,  Brian Gerard Holthaus ,  Daniel Robert Lipps ,  Daniel Frank Moertl ,  Paul Edward Movall ,  Daniel Paul Wetzel

    发明人： Ellen Marie Bauman ,  David Lee Dosch ,  Charles Scott Graham ,  Brian Gerard Holthaus ,  Daniel Robert Lipps ,  Daniel Frank Moertl ,  Paul Edward Movall ,  Daniel Paul Wetzel

    IPC分类号： G06F1300

    CPC分类号： G06F13/404

    摘要： A method and apparatus are provided for mapping multiple address spaces into a single bus, such as a single peripheral component interconnect (PCI) bus. The single bus is coupled to a first processor complex and a second processor complex. An original address of a memory access is shifted to a unique address space for each originator/target of an operation. The shifted address is used on the single bus. Then the shifted address is shifted back to the original address for completing the operation on a destination bus. The original address of a memory access is shifted to a unique address space for each originator/target of an operation using a respective predefined value (+X1, +X2, or +X3) for shifting the original address above a predefined boundary for each originator/target of the operation. Shifting back the shifted address to the original address for completing the operation on the destination bus uses a respective predefined value (−X1, −X2, or −X3) for the shifted back address to the original address for completing the operation on the destination bus. Using the shifted address on the single bus utilizes a dual address cycle (DAC) of the single bus for the shifted address. Completing the operation on a destination bus utilizes a single address cycle (SAC) of the destination bus for the shifted back address to the original address.

    摘要翻译： 提供了一种用于将多个地址空间映射到单个总线（诸如单个外围组件互连（PCI）总线）的方法和装置。 单总线耦合到第一处理器复合体和第二处理器复合体。 存储器访问的原始地址被移动到操作的每个发起者/目标的唯一地址空间。 移位的地址用于单总线。 然后将移位的地址移回原始地址，以完成目标总线上的操作。 使用相应的预定义值（+ X1，+ X2或+ X3）将存储器访问的原始地址移动到每个发起者/目标的唯一地址空间，用于将原始地址移动到每个发起者的预定边界之上 /目标的操作。 将移动的地址移动到原始地址以完成目的地总线上的操作，将移位后地址的相应预定义值（-X1，-X2或-X3）用于原始地址，以完成目标总线上的操作 。 使用单总线上的移位地址，可以使用单总线的双地址周期（DAC）作为移位地址。 在目的地总线上完成操作将目的地总线的单个地址周期（SAC）用于移位后地址到原始地址。

    Heterogeneous system enclosure services connection
    5.
    发明授权
    Heterogeneous system enclosure services connection 有权
    异构系统机箱服务连接

    公开(公告)号：US06351819B1

    公开(公告)日：2002-02-26

    申请号：US09267778

    申请日：1999-03-15

    申请人： Neil Clair Berglund ,  Ronald Leroy Billau ,  David Lee Dosch ,  Brian Gerard Holthaus ,  Thomas James Osten ,  Frederick Joseph Ziecina

    发明人： Neil Clair Berglund ,  Ronald Leroy Billau ,  David Lee Dosch ,  Brian Gerard Holthaus ,  Thomas James Osten ,  Frederick Joseph Ziecina

    IPC分类号： G06F126

    CPC分类号： H04L41/00 ,  G06F1/26

    摘要： An adapter node is provided for use in adapting internal system enclosure services to a system power control network to thereby provide remote power control, diagnostics, and logical-to-physical correlation information, through the system power control network. The adapter node is for use in one computer of a plurality of different types of computers, having a respective internal system enclosure services low-level communication path. The power control network has a plurality of nodes, one of the nodes being a control node. The adapter node includes a substrate having electrical contacts adapted to plug to a system bus in the one computer. The substrate further has at least one system enclosure services interface connection to connect to the internal system enclosure services low-level communication path in the one computer. The adapter node further has a system power control network interface connection for connecting to the system power control network. A processor of the adapter node is provided for coordinating communication with the system power control network and with internal devices on the internal system enclosure services low-level communications path. Power control, diagnostics, and logical-to-physical correlation information signals are communicated between the system power control system control node and the adapter node to provide system enclosure services support to the one computer of the plurality of different types of computers.

    摘要翻译： 提供适配器节点，用于将内部系统机箱服务适配到系统功率控制网络，从而通过系统功率控制网络提供远程功率控制，诊断和逻辑到物理相关信息。 适配器节点用于多个不同类型的计算机的一台计算机，具有相应的内部系统机箱服务低级通信路径。 功率控制网络具有多个节点，其中一个节点是控制节点。 适配器节点包括具有适于在一台计算机中插入系统总线的电触点的基板。 基板还具有至少一个系统机箱服务接口连接，以连接到一个计算机中的内部系统机箱服务低级通信路径。 适配器节点还具有用于连接到系统功率控制网络的系统功率控制网络接口连接。 适配器节点的处理器被提供用于协调与系统功率控制网络的通信以及内部系统机箱上的内部设备服务低级通信路径。 功率控制，诊断和逻辑到物理相关信息信号在系统功率控制系统控制节点和适配器节点之间通信，以向多个不同类型的计算机中的一个计算机提供系统机箱服务支持。

    Method and apparatus for interrupt routing of PCI adapters via device address mapping
    6.
    发明授权
    Method and apparatus for interrupt routing of PCI adapters via device address mapping 失效
    通过设备地址映射中断PCI适配器路由的方法和装置

    公开(公告)号：US06643724B2

    公开(公告)日：2003-11-04

    申请号：US09748980

    申请日：2000-12-27

    申请人： Ellen Marie Bauman ,  David Lee Dosch ,  Daniel Paul Wetzel

    发明人： Ellen Marie Bauman ,  David Lee Dosch ,  Daniel Paul Wetzel

    IPC分类号： G06F1324

    CPC分类号： G06F13/24

    摘要： A method and apparatus are provided for interrupt routing of peripheral component interconnect (PCI) adapters via device address mapping. A first processor complex includes a multifunction PCI to PCI bridge interface chip. A local PCI bus is coupled between a second processor complex and the multifunction PCI to PCI bridge interface chip. A host PCI bus is coupled between the multifunction PCI to PCI bridge interface chip and a second multifunction PCI to PCI bridge chip. A plurality of local area network (LAN) adapters are coupled to the second multifunction PCI to PCI bridge chip. The multifunction PCI to PCI bridge interface chip of the first processor complex includes interrupt mapping logic for mapping interrupts from the LAN adapters to PCI interrupts on the local PCI bus to the second processor complex. The multifunction PCI to PCI bridge interface chip of the first processor complex includes translation logic for translating a configuration cycle on the local PCI bus from the second processor complex to another configuration cycle on the host PCI bus and for translating a configuration cycle on the host PCI bus from the LAN adapters to another configuration cycle on the local PCI bus to the second processor complex. The multifunction PCI to PCI bridge interface chip of the first processor complex includes a bus number register for specifying a PCI bus number and a device translation register for specifies a translation value for each function of the multifunction PCI to PCI bridge interface chip for determining a device number of each of said plurality of local area network (LAN) adapters.

    摘要翻译： 提供了一种用于通过设备地址映射来中断路由外围组件互连（PCI）适配器的方法和装置。 第一个处理器组合包括一个多功能PCI到PCI桥接口芯片。 本地PCI总线耦合在第二处理器复合体和多功能PCI至PCI桥接口芯片之间。 主机PCI总线耦合在多功能PCI至PCI桥接口芯片和第二个多功能PCI至PCI桥接芯片之间。 多个局域网（LAN）适配器耦合到第二多功能PCI至PCI桥芯片。 第一处理器复合体的多功能PCI至PCI桥接器芯片包括用于将局域网适配器的中断映射到本地PCI总线上的PCI中断到第二处理器复合体的中断映射逻辑。 第一处理器复合体的多功能PCI至PCI桥接口芯片包括翻译逻辑，用于将本地PCI总线上的配置周期从第二处理器复合转换到主机PCI总线上的另一个配置周期，并用于翻译主机PCI上的配置周期 总线从LAN适配器到本地PCI总线上的另一个配置周期到第二个处理器组合。 第一处理器复合体的多功能PCI至PCI桥接口芯片包括用于指定PCI总线号的总线号寄存器和用于指定用于确定设备的多功能PCI至PCI桥接器芯片的每个功能的转换值的设备转换寄存器 所述多个局域网（LAN）适配器中的每一个的数量。