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103 条记录 (耗时 0.025 秒)

    Methods and systems for improving a maximum operating frequency of an integrated circuit during a route phase
    3.
    发明授权
    Methods and systems for improving a maximum operating frequency of an integrated circuit during a route phase 有权
    用于在路线阶段期间提高集成电路的最大工作频率的方法和系统

    公开(公告)号：US08191028B1

    公开(公告)日：2012-05-29

    申请号：US12419986

    申请日：2009-04-07

    申请人： Mark Bourgeault ,  Vaughn Betz

    发明人： Mark Bourgeault ,  Vaughn Betz

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5077

    摘要： Mechanisms are provided to improve maximum operating frequency in an integrated circuit. Optimization may be performed during a route phase of a compilation process performed to generate a configuration of the integrated circuit. In some instances, useful clock skew is automatically determined and clock connectivity is rewired on a per-integrated circuit block (per-LAB) basis during the route phase.

    摘要翻译： 提供了用于提高集成电路中的最大工作频率的机制。 可以在执行用于生成集成电路的配置的编译处理的路由阶段期间执行优化。 在某些情况下，在路由阶段期间，自动确定有用的时钟偏移，并在每个集成电路块（每个LAB）上重新布线时钟连接。

    Method and apparatus for implementing cross-talk based booster wires in a system on a field programmable gate array
    5.
    发明授权
    Method and apparatus for implementing cross-talk based booster wires in a system on a field programmable gate array 有权
    用于在现场可编程门阵列上的系统中实现基于串扰的升压线的方法和装置

    公开(公告)号：US08468487B1

    公开(公告)日：2013-06-18

    申请号：US12386739

    申请日：2009-04-22

    申请人： Zahir Parpia ,  Chris Wysocki ,  Vaughn Betz

    发明人： Zahir Parpia ,  Chris Wysocki ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F17/5077

    摘要： A method for designing a system on a field programmable gate array (FPGA) includes routing one or more booster wires alongside an interconnect to reduce a delay of a signal being transmitted on the interconnect. According to one aspect of the present invention, the routing of the one or more booster wires is performed in response to determining that a timing requirement of the system has not been met.

    摘要翻译： 用于在现场可编程门阵列（FPGA）上设计系统的方法包括在互连旁边布置一个或多个升压线，以减少在互连上传输的信号的延迟。 根据本发明的一个方面，响应于确定尚未满足系统的定时要求，执行一个或多个升压线的路由。

    Clock switch-over circuits and methods
    6.
    发明授权
    Clock switch-over circuits and methods 有权
    时钟切换电路和方法

    公开(公告)号：US08248110B1

    公开(公告)日：2012-08-21

    申请号：US13048241

    申请日：2011-03-15

    申请人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz ,  Marcel A. LeBlanc

    发明人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz ,  Marcel A. LeBlanc

    IPC分类号： H01H71/22

    CPC分类号： G06F1/10

    摘要： Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.

    摘要翻译： 时钟切换电路和方法为时钟路由网络提供时钟信号。 根据一个实施例，多路复用器响应于从控制电路接收的开关选择信号在第一时钟信号和第二时钟信号之间进行选择。 存储电路响应于多路复用器的输出时钟信号而存储使能信号。 响应于来自存储电路的使能信号，逻辑电路将多路复用器的输出时钟信号传输到时钟路由网络。 至少一个信号从时钟切换电路发送到控制电路。

    Method and apparatus for performing parallel routing using a multi-threaded routing procedure
    7.
    发明申请
    Method and apparatus for performing parallel routing using a multi-threaded routing procedure 有权
    使用多线程路由过程执行并行路由的方法和装置

    公开(公告)号：US20100169858A1

    公开(公告)日：2010-07-01

    申请号：US12317789

    申请日：2008-12-29

    申请人： Vaughn Betz ,  Jordan Swartz ,  Vadim Gouterman

    发明人： Vaughn Betz ,  Jordan Swartz ,  Vadim Gouterman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

    摘要翻译： 一种用于设计要在目标设备上实现的系统的方法包括在系统中为网络生成目标设备上的边界框，其中边界框标识可用于路由其相应网络的路由资源。 系统中的网络被分配给要路由的多个线程。 执行线程使得多个网络在其对应的边界框内并行路由。

    Efficient delay elements
    8.
    发明授权
    Efficient delay elements 有权
    高效延时元件

    公开(公告)号：US07659764B2

    公开(公告)日：2010-02-09

    申请号：US12212314

    申请日：2008-09-17

    申请人： Ryan Fung ,  Vaughn Betz

    发明人： Ryan Fung ,  Vaughn Betz

    IPC分类号： H03K3/00

    CPC分类号： H03K19/17736 ,  H03K5/133 ,  H03K19/1778 ,  H03K19/17792 ,  H03K2005/00058 ,  H03K2005/00234

    摘要： Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components with differing delays that may be combined to give flexibility in choices for delay increments while minimizing the area of the delay element. A delay element is shared between different signal paths, for example, to reduce the number of delay elements or to allow utilizing unused delay elements of other signal paths.

    摘要翻译： 提供了用于以功率和区域有效的方式延迟信号的电路，方法和装置。 可编程延迟元件的级内的门控元件抑制延迟元件的其他级的操作。 可编程延迟具有不同延迟的组件，其可以组合以在延迟增量的选择中提供灵活性，同时最小化延迟元件的面积。 延迟元件在不同的信号路径之间被共享，例如，以减少延迟元件的数量或允许利用其他信号路径的未使用的延迟元件。

    Distributed memory in field-programmable gate array integrated circuit devices
    9.
    发明授权
    Distributed memory in field-programmable gate array integrated circuit devices 有权
    现场可编程门阵列集成电路器件中的分布式存储器

    公开(公告)号：US07656191B2

    公开(公告)日：2010-02-02

    申请号：US12156403

    申请日：2008-05-30

    申请人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    发明人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    IPC分类号： H03K19/177

    CPC分类号： G11C7/1045 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

    摘要： Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

    摘要翻译： 用于便于将现场可编程门阵列（“FPGA”）的查找表（“LUT”）中的存储元件用作用户可访问的分布式RAM的电路。 例如，可以使用与用户RAM模式中的与LUT相关联并且在读取数据路径中不需要的寄存器来登记用于用户RAM模式的写入数据。 作为另一示例，可以使用与LUT相关联的另外不需要的寄存器来提供用于用户RAM模式的同步读取地址信号。 显示了几个其他功能，用于在FPGA中需要最少（如果有的话）附加电路的同时方便用户RAM模式。

    Computer-aided-design tools for reducing power consumption in programmable logic devices
    10.
    发明授权
    Computer-aided-design tools for reducing power consumption in programmable logic devices 有权
    用于降低可编程逻辑器件功耗的计算机辅助设计工具

    公开(公告)号：US07555741B1

    公开(公告)日：2009-06-30

    申请号：US11520944

    申请日：2006-09-13

    申请人： David Ian M. Milton ,  David Neto ,  Vaughn Betz

    发明人： David Ian M. Milton ,  David Neto ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F2217/78

    摘要： Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to analyze various implementations of a desired logic design for a programmable logic device integrated circuit. The logic design system may be used to produce configuration data for the programmable logic device in accordance with an implementation that minimizes power consumption by the programmable logic device. The programmable logic device contains logic blocks that are used to implement the desired logic design and logic blocks that are unused. Dynamic power consumption can be minimized by identifying which configuration data settings reduce the amount of signal toggling in the unused logic blocks and routing, and by minimizing the capacitance of resources that do toggle. Clock tree power consumption can be reduced by evaluating multiple potential logic design implementations using a strictly concave cost function.

    摘要翻译： 提供了设计和制造可编程逻辑器件的方法和设备。 可以使用逻辑设计系统来分析用于可编程逻辑器件集成电路的期望逻辑设计的各种实现。 逻辑设计系统可以用于根据使可编程逻辑器件的功耗最小化的实现来产生可编程逻辑器件的配置数据。 可编程逻辑器件包含用于实现未使用的所需逻辑设计和逻辑块的逻辑块。 可以通过识别哪些配置数据设置减少未使用的逻辑块和路由中的信号切换量以及通过最小化切换的资源的电容来最小化动态功耗。 通过使用严格的凹成本函数评估多个潜在的逻辑设计实现，可以减少时钟树的功耗。