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公开(公告)号：US20210382987A1
公开(公告)日：2021-12-09
申请号：US17407035
申请日：2021-08-19
申请人： Vedvyas Shanbhogue , Jason W. Brandt , Ravi L. Sahita , Barry E. Huntley , Baiju V. Patel , Deepak K. Gupta
发明人： Vedvyas Shanbhogue , Jason W. Brandt , Ravi L. Sahita , Barry E. Huntley , Baiju V. Patel , Deepak K. Gupta
摘要： A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.
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公开(公告)号：US10515023B2
公开(公告)日：2019-12-24
申请号：US15088739
申请日：2016-04-01
申请人： Ravi L. Sahita , Gilbert Neiger , Vedvyas Shanbhogue , David M. Durham , Andrew V. Anderson , David A. Koufaty , Asit K. Mallick , Arumugam Thiyagarajah , Barry E. Huntley , Deepak K. Gupta , Michael Lemay , Joseph F. Cihula , Baiju V. Patel
发明人： Ravi L. Sahita , Gilbert Neiger , Vedvyas Shanbhogue , David M. Durham , Andrew V. Anderson , David A. Koufaty , Asit K. Mallick , Arumugam Thiyagarajah , Barry E. Huntley , Deepak K. Gupta , Michael Lemay , Joseph F. Cihula , Baiju V. Patel
IPC分类号： G06F12/00 , G06F12/14 , G06F12/1009 , G06F9/455 , G06F12/1027 , G06F21/78
摘要： This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.
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公开(公告)号：US07902073B2
公开(公告)日：2011-03-08
申请号：US11610953
申请日：2006-12-14
申请人： Ji Soo Kim , Sangheon Lee , Deepak K. Gupta , S. M. Reza Sadjadi
发明人： Ji Soo Kim , Sangheon Lee , Deepak K. Gupta , S. M. Reza Sadjadi
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/30655 , H01L21/31116 , H01L21/312
摘要： A method for etching features in an etch layer disposed below a mask on a process wafer is provided. A hydrocarbon based glue layer is deposited. The etch layer on the process wafer is etched with at least one cycle, wherein each cycle comprises depositing a hydrofluorocarbon layer over the mask and on the hydrocarbon based glue layer, wherein the hydrocarbon based glue layer increases adhesion of the hydrofluorocarbon layer and etching the etch layer.
摘要翻译： 提供了一种用于蚀刻设置在处理晶片上的掩模下方的蚀刻层中的特征的方法。 沉积烃基胶层。 用至少一个循环蚀刻处理晶片上的蚀刻层，其中每个循环包括在掩模上和基于烃的胶层上沉积氢氟碳化合物层，其中基于烃的胶层增加氢氟烃层的粘附和蚀刻蚀刻 层。
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公开(公告)号：US20170249260A1
公开(公告)日：2017-08-31
申请号：US15088739
申请日：2016-04-01
申请人： RAVI L. SAHITA , GILBERT NEIGER , VEDVYAS SHANBHOGUE , DAVID M. DURHAM , ANDREW V. ANDERSON , DAVID A. KOUFATY , ASIT K. MALLICK , ARUMUGAM THIYAGARAJAH , BARRY E. HUNTLEY , DEEPAK K. GUPTA , MICHAEL LEMAY , JOSEPH F. CIHULA , BAIJU V. PATEL
发明人： RAVI L. SAHITA , GILBERT NEIGER , VEDVYAS SHANBHOGUE , DAVID M. DURHAM , ANDREW V. ANDERSON , DAVID A. KOUFATY , ASIT K. MALLICK , ARUMUGAM THIYAGARAJAH , BARRY E. HUNTLEY , DEEPAK K. GUPTA , MICHAEL LEMAY , JOSEPH F. CIHULA , BAIJU V. PATEL
摘要： This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.
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公开(公告)号：US20080146032A1
公开(公告)日：2008-06-19
申请号：US11610953
申请日：2006-12-14
申请人： Ji Soo Kim , Sangheon Lee , Deepak K. Gupta , S. M. Reza Sadjadi
发明人： Ji Soo Kim , Sangheon Lee , Deepak K. Gupta , S. M. Reza Sadjadi
IPC分类号： H01L21/3105
CPC分类号： H01L21/31144 , H01L21/30655 , H01L21/31116 , H01L21/312
摘要： A method for etching features in an etch layer disposed below a mask on a process wafer is provided. A hydrocarbon based glue layer is deposited. The etch layer on the process wafer is etched with at least one cycle, wherein each cycle comprises depositing a hydrofluorocarbon layer over the mask and on the hydrocarbon based glue layer, wherein the hydrocarbon based glue layer increases adhesion of the hydrofluorocarbon layer and etching the etch layer.
摘要翻译： 提供了一种用于蚀刻设置在处理晶片上的掩模下方的蚀刻层中的特征的方法。 沉积烃基胶层。 用至少一个循环蚀刻处理晶片上的蚀刻层，其中每个循环包括在掩模上和基于烃的胶层上沉积氢氟烃层，其中基于烃的胶层增加氢氟烃层的粘附和蚀刻蚀刻 层。
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