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    Joint encoding of logical pages in multi-page memory architecture
    2.
    发明授权
    Joint encoding of logical pages in multi-page memory architecture 有权
    在多页内存架构中对逻辑页进行联合编码

    公开(公告)号：US08254167B2

    公开(公告)日：2012-08-28

    申请号：US12781774

    申请日：2010-05-17

    申请人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce D. Buch

    发明人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce D. Buch

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C29/00 ,  G11C2216/14

    摘要： Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of the multi-level memory cells while a second logical page of the multiple logical pages is temporarily cached. After the first logical page is stored as the first bits of the memory cell, the second logical page is stored as second bits of the memory cells.

    摘要翻译： 多个逻辑页面被联合编码成单个码字，并被存储在具有多层存储器单元的固态非易失性存储器（NVM）设备的相同物理页面中。 多个逻辑页面的第一逻辑页面被存储在存储器设备中作为多级存储器单元的第一位，而多个逻辑页面的第二逻辑页面被临时高速缓存。 在将第一逻辑页面存储为存储器单元的第一位之后，第二逻辑页面被存储为存储器单元的第二位。

    ITERATIVE DEMODULATION AND DECODING FOR MULTI-PAGE MEMORY ARCHITECTURE
    4.
    发明申请
    ITERATIVE DEMODULATION AND DECODING FOR MULTI-PAGE MEMORY ARCHITECTURE 有权
    多媒体存储器架构的迭代解码和解码

    公开(公告)号：US20110280069A1

    公开(公告)日：2011-11-17

    申请号：US12781780

    申请日：2010-05-17

    申请人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce D. Buch

    发明人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce D. Buch

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C11/5642 ,  G11C2029/0411

    摘要： Methods and systems for accessing encoded data stored in a solid state non-volatile memory device include iteratively demodulating and decoding the data. The memory device includes memory cells arranged to store multiple bits of data per memory cell. The memory cells are capable of storing multiple pages of data. Each bit stored in a memory cell is associated with a page of data that is different from other pages associated with other bits stored in the memory cell. The multiple pages are demodulated responsive to sensed voltage levels of the memory cells, and a demodulated output is provided for each page of the multiple pages. A decoded output for each page of the multiple pages is generated. Decoding the page and demodulating the multiple pages proceeds iteratively, including an exchange of information between the decoder and the demodulator.

    摘要翻译： 访问存储在固态非易失性存储器件中的编码数据的方法和系统包括对数据进行迭代解调和解码。 存储器件包括存储器单元，其被布置为存储每个存储器单元的多个位数据。 存储单元能够存储多页数据。 存储在存储器单元中的每个位与与存储在存储单元中的其它位相关的其它页不同的数据页相关联。 响应于感测的存储器单元的电压电平对多页进行解调，并且为多页的每一页提供解调输出。 生成多页的每一页的解码输出。 对页面进行解码并解调多个页面进行迭代，包括解码器和解调器之间的信息交换。

    Iterative demodulation and decoding for multi-page memory architecture
    6.
    发明授权
    Iterative demodulation and decoding for multi-page memory architecture 有权
    用于多页存储器架构的迭代解调和解码

    公开(公告)号：US08406051B2

    公开(公告)日：2013-03-26

    申请号：US12781780

    申请日：2010-05-17

    申请人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce D. Buch

    发明人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce D. Buch

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5642 ,  G11C2029/0411

    摘要： Methods and systems for accessing encoded data stored in a solid state non-volatile memory device include iteratively demodulating and decoding the data. The memory device includes memory cells arranged to store multiple bits of data per memory cell. The memory cells are capable of storing multiple pages of data. Each bit stored in a memory cell is associated with a page of data that is different from other pages associated with other bits stored in the memory cell. The multiple pages are demodulated responsive to sensed voltage levels of the memory cells, and a demodulated output is provided for each page of the multiple pages. A decoded output for each page of the multiple pages is generated. Decoding the page and demodulating the multiple pages proceeds iteratively, including an exchange of information between the decoder and the demodulator.

    摘要翻译： 访问存储在固态非易失性存储器件中的编码数据的方法和系统包括对数据进行迭代解调和解码。 存储器件包括存储器单元，其被布置为存储每个存储器单元的多个位数据。 存储单元能够存储多页数据。 存储在存储器单元中的每个位与与存储在存储单元中的其它位相关的其它页不同的数据页相关联。 响应于感测的存储器单元的电压电平对多页进行解调，并且为多页的每一页提供解调输出。 生成多页的每一页的解码输出。 对页面进行解码并解调多个页面进行迭代，包括解码器和解调器之间的信息交换。

    JOINT ENCODING OF LOGICAL PAGES IN MULTI-PAGE MEMORY ARCHITECTURE
    7.
    发明申请
    JOINT ENCODING OF LOGICAL PAGES IN MULTI-PAGE MEMORY ARCHITECTURE 有权
    多页存储器架构中逻辑页面的编辑

    公开(公告)号：US20110280068A1

    公开(公告)日：2011-11-17

    申请号：US12781774

    申请日：2010-05-17

    申请人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce Buch

    发明人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce Buch

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C29/00 ,  G11C2216/14

    摘要： Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of the multi-level memory cells while a second logical page of the multiple logical pages is temporarily cached. After the first logical page is stored as the first bits of the memory cell, the second logical page is stored as second bits of the memory cells.

    摘要翻译： 多个逻辑页面被联合编码成单个码字，并被存储在具有多层存储器单元的固态非易失性存储器（NVM）设备的相同物理页面中。 多个逻辑页面的第一逻辑页面被存储在存储器设备中作为多级存储器单元的第一位，而多个逻辑页面的第二逻辑页面被临时高速缓存。 在将第一逻辑页面存储为存储器单元的第一位之后，第二逻辑页面被存储为存储器单元的第二位。