公开(公告)号：US20230208448A1

公开(公告)日：2023-06-29

申请号：US17562105

申请日：2021-12-27

申请人： Western Digital Technologies, Inc.

发明人： David AVRAHAM ,  Ran ZAMIR ,  Alexander BAZARSKY

IPC分类号： H03M13/00 ,  G06F11/10

CPC分类号： H03M13/6577 ,  G06F11/1068

摘要： A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine an error correction code (ECC) code length for KV pair data and/or an ECC code rate for the KV pair data, where the ECC code length and the ECC code rate are selected according to a value length and decoding capability of the KV pair data, generate ECC parity based on the selecting, and program the KV pair data and the generated ECC parity to the memory device.

公开(公告)号：US20180062666A1

公开(公告)日：2018-03-01

申请号：US15244444

申请日：2016-08-23

申请人： SANDISK TECHNOLOGIES LLC

发明人： XINMIAO ZHANG ,  ALEXANDER BAZARSKY ,  RAN ZAMIR ,  ERAN SHARON ,  IDAN ALROD ,  OMER FAINZILBER ,  SANEL ALTERMAN

IPC分类号： H03M13/11 ,  G06F11/10 ,  G11C29/52

CPC分类号： G06F11/1068 ,  G11C2029/0411 ,  H03M13/1122 ,  H03M13/114 ,  H03M13/116 ,  H03M13/6502 ,  H03M13/6577

摘要： In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.

公开(公告)号：US20160241257A1

公开(公告)日：2016-08-18

申请号：US15042365

申请日：2016-02-12

申请人： Chris Winstead ,  Emmanuel Boutillon

发明人： Chris Winstead ,  Emmanuel Boutillon

IPC分类号： H03M13/11 ,  H03M13/37

CPC分类号： H03M13/1108 ,  H03M13/1117 ,  H03M13/451 ,  H03M13/6577

摘要： For decoding messages, a decoder exchanges single-bit messages for a data channel between a plurality of M parity nodes and a plurality of N symbol nodes. Each parity node has one or more adjacent symbol nodes with a plurality of edges between the parity node and each adjacent symbol node. An extrinsic decision and an extrinsic parity value are calculated based on a time-varying lookup table. The lookup table stores the locally maximum-likelihood extrinsic decision for a quantized number of data channel states as a function of adjacent extrinsic parity values.

摘要翻译： 对于解码消息，解码器为多个M个奇偶校验节点和多个N个符号节点之间的数据信道交换单位消息。 每个奇偶校验节点具有一个或多个相邻符号节点，其中奇偶校验节点和每个相邻符号节点之间具有多个边。 基于时变查询表计算外在判定和外在奇偶校验值。 查找表存储用于量化数量的数据信道状态的局部最大似然外在判定，作为相邻外在奇偶校验值的函数。

公开(公告)号：US09337955B2

公开(公告)日：2016-05-10

申请号：US13965508

申请日：2013-08-13

申请人： Apple Inc.

发明人： Micha Anholt ,  Naftali Sommer

IPC分类号： H03M13/00 ,  H04L1/00 ,  H03M13/11 ,  H03M13/37

CPC分类号： H04L1/004 ,  H03M13/1111 ,  H03M13/3776 ,  H03M13/6502 ,  H03M13/6577

摘要： A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word.

公开(公告)号：US20150295592A1

公开(公告)日：2015-10-15

申请号：US14686629

申请日：2015-04-14

申请人： Samsung Electronics Co., Ltd

发明人： Seok-Ki Ahn ,  Kyeong-Cheol Yang ,  Sang-Min Kim ,  Woo-Myoung Park ,  Min Sagong ,  Chi-Woo Lim ,  Sung-Nam Hong

IPC分类号： H03M13/11

CPC分类号： H03M13/1171 ,  H03M13/1117 ,  H03M13/6502 ,  H03M13/6577

摘要： Provided is a method for decoding a non-binary (NB) low density parity check (LDPC) code at a user equipment (UE) that implements at least one variable nodes that receive a received signal of a wireless channel and deliver an input message to a check node and the check node that checks the input message and outputs an output message. The method includes receiving at least one input messages, generating a temporary vector by using the at least one input messages, searching for an element having a dominant value by checking the temporary vector, generating a configuration set, which is a check target, by using the element having the dominant value, and generating the output message by performing comparison with respect to the generated configuration set.

摘要翻译： 提供了一种用于在实现至少一个可变节点的用户设备（UE）处对非二进制（NB）低密度奇偶校验（LDPC）码进行解码的方法，该可变节点接收无线信道的接收信号并将输入消息传送到 检查节点和检查节点，其检查输入消息并输出输出消息。 该方法包括接收至少一个输入消息，通过使用至少一个输入消息生成临时向量，通过检查临时向量来搜索具有主导值的元素，生成作为检查对象的配置集，通过使用 所述元件具有所述主导值，并且通过对所生成的配置集执行比较来生成所述输出消息。

公开(公告)号：US08984378B1

公开(公告)日：2015-03-17

申请号：US14204711

申请日：2014-03-11

申请人： Marvell International Ltd.

发明人： Shashi Kiran Chilappagari ,  Nedeljko Varnica ,  Xueshi Yang ,  Gregory Burd

IPC分类号： H03M13/00 ,  H03M13/11

CPC分类号： H03M13/1108 ,  H03M13/1137 ,  H03M13/6577

摘要： Systems and methods are provided for decoding data using hard decisions and soft information. In particular, the systems and methods described herein are directed to decoders having variable nodes and check nodes, each with multiple states. The systems and methods include receiving, at a decoder during a first iteration, values for each of a plurality of variable nodes, and determining, during a second iteration, one or more indications for each of a plurality of check nodes based on the one or more values of the variable nodes received during the first iteration. The methods further include updating, at the decoder during the second iteration, the values for each of the variable nodes based on the values of the respective variable node received during the first iteration, and the indications for each of the plurality connected check nodes during the first iteration.

摘要翻译： 提供了使用硬判决和软信息对数据进行解码的系统和方法。 特别地，这里描述的系统和方法涉及具有可变节点和校验节点的解码器，每个具有多个状态。 所述系统和方法包括在第一次迭代期间在解码器处接收多个变量节点中的每一个的值，以及在第二迭代期间，基于所述一个或多个节点在多个检查节点中的每一个确定一个或多个指示 在第一次迭代期间接收到的变量节点的更多值。 所述方法还包括在第二次迭代期间在解码器处更新基于在第一次迭代期间接收到的相应可变节点的值的每个变量节点的值，以及在该第一迭代期间针对多个连接的校验节点中的每一个的指示 第一次迭代

公开(公告)号：US08856625B2

公开(公告)日：2014-10-07

申请号：US13601186

申请日：2012-08-31

申请人： Daisuke Miyashita

发明人： Daisuke Miyashita

IPC分类号： H03M13/00

CPC分类号： G06F11/1008 ,  H03M5/08 ,  H03M13/1117 ,  H03M13/6502 ,  H03M13/6577

摘要： A decoding device is provided for decoding received data which is coded based on low-density parity-check code. The decoding device includes a variable node operation unit, a check node operation unit, and a circuit in the transmission path between the two units. The variable node operation unit generates secondary probability information based on primary probability information and the coded data. The check node operation unit generates the primary probability information based on the secondary probability information. The circuit transmits the primary probability information and the secondary probability information between the variable node operation unit and the check node operation unit. In addition, at least one of the primary probability information and the secondary probability information transmitted via the transmission path is represented by a time signal.

摘要翻译： 提供了一种解码装置，用于对基于低密度奇偶校验码进行编码的接收数据进行解码。 解码装置包括可变节点操作单元，校验节点操作单元和两个单元之间的传输路径中的电路。 可变节点操作单元基于主概率信息和编码数据生成二次概率信息。 校验节点操作单元基于次要概率信息生成主概率信息。 电路在可变节点运算单元和校验节点运算单元之间传输主要概率信息和次要概率信息。 此外，经由传输路径发送的主要概率信息和次要概率信息中的至少一个由时间信号表示。

公开(公告)号：US20140298142A1

公开(公告)日：2014-10-02

申请号：US14303280

申请日：2014-06-12

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kenji SAKAUE ,  Atsushi TAKAYAMA ,  Yoshihisa KONDO ,  Tatsuyuki ISHIKAWA

IPC分类号： G06F11/10

CPC分类号： G06F11/1068 ,  G06F11/1048 ,  G11C29/00 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/1177 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/45 ,  H03M13/6502 ,  H03M13/6505 ,  H03M13/6577

摘要： A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information β calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information β stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.

摘要翻译： 一种存储器控制器，包括：缓冲器，被配置为基于由单位矩阵的块和多个块组成的校验矩阵，通过部分并行处理来执行由LDPC解码器解码的帧单元数据，其中，每行单位矩阵 顺序地移位并存储从存储器部分读取的数据的阈值判定信息，被配置为将阈值判定信息转换为LLR的LLR转换部分，被配置为存储概率信息＆lt; bgr的LMEM; 在迭代处理期间计算的重复执行列处理和基于等于或小于块的大小的迭代单元中的LLR的行处理以及被配置为传送概率信息＆bgr的CPU核心; 每次迭代单元中的迭代处理完成时，将LMEM存储在缓冲区中。

公开(公告)号：US08677227B2

公开(公告)日：2014-03-18

申请号：US13216373

申请日：2011-08-24

申请人： Warren Gross ,  Saied Hemati ,  Shie Mannor ,  Ali Naderi ,  Francois Leduc-Primeau

发明人： Warren Gross ,  Saied Hemati ,  Shie Mannor ,  Ali Naderi ,  Francois Leduc-Primeau

IPC分类号： G06F11/10 ,  H03M13/00

CPC分类号： H03M13/6544 ,  H03M13/1117 ,  H03M13/1137 ,  H03M13/1142 ,  H03M13/1151 ,  H03M13/3707 ,  H03M13/6575 ,  H03M13/6577

摘要： Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with code length. They also offer challenges relating to decoding complexity and error floors limiting achievable bit-error rates. Accordingly encoders with reduced complexity, reduced power consumption and improved performance are disclosed with various improvements including simplifying communications linking multiple processing nodes by passing messages where pulse widths are modulated with the corresponding message magnitude, delaying a check operation in dependence upon variable node states, running the decoder multiple times with different random number generator seeds for a constant channel value set, and employing a second decoder with a randomizing component when the attempt with the first decoder fails.

摘要翻译： 低密度奇偶校验（LDPC）码在接近链路信道容量的速率下提供误码校正，并且在存在数据破坏噪声的带宽或返回信道受限链路上进行可靠和有效的信息传输。 它们还提供了在代码长度，线性处理复杂度以及与代码长度相关联的并行性方面，指数速度接近通道容量的性能。 它们还提供与解码复杂性和错误底层限制可实现的误码率有关的挑战。 因此，具有降低的复杂性，降低的功耗和改进的性能的编码器被公开，其具有各种改进，包括简化通过传递消息，其中脉冲宽度被调制与相应的消息幅度相关联的通信，延迟根据变量节点状态的检查操作， 解码器多次具有用于恒定信道值集合的不同随机数发生器种子，并且当第一解码器的尝试失败时，采用具有随机化分量的第二解码器。

公开(公告)号：US20140053044A1

公开(公告)日：2014-02-20

申请号：US14112396

申请日：2013-04-01

申请人： Panasonic Corporation

发明人： Tsuyoshi Nakasendo ,  Yasumori Hino ,  Kohei Nakata ,  Yuji Takagi

IPC分类号： G06F11/10

CPC分类号： G06F11/10 ,  G11B20/10361 ,  G11B20/1833 ,  H03M13/1111 ,  H03M13/2957 ,  H03M13/45 ,  H03M13/6343 ,  H03M13/6577

摘要： A decoding device (1) has: a reliability calculating unit (5) which calculates reliability information having a non-linear relationship with a noise distribution of a PR communication path (3) in at least part of or all of the reliability information based on characteristics of the PR communication path (3) and a predetermined modulation rule from an encoded signal that is obtained from the PR communication path (3); a reliability correcting unit (17) which corrects the reliability information calculated by a reliability calculating unit (5); and an error correction decoding unit (18) which performs error correction decoding on the reliability information corrected by the reliability correcting unit (17).

摘要翻译： 一种解码装置（1）具有：可靠性计算部（5），在至少一部分或全部可靠性信息中，根据PR通信路径（3）的噪声分布，计算与所述PR通信路径（3）的噪声分布具有非线性关系的可靠性信息 PR通信路径（3）的特征和来自PR通信路径（3）获得的编码信号的预定调制规则; 可靠性校正单元，其校正由可靠性计算单元计算出的可靠性信息; 以及对由可靠性校正单元（17）校正的可靠性信息执行纠错解码的纠错解码单元（18）。