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    Iterative demodulation and decoding for multi-page memory architecture
    3.
    发明授权
    Iterative demodulation and decoding for multi-page memory architecture 有权
    用于多页存储器架构的迭代解调和解码

    公开(公告)号：US08406051B2

    公开(公告)日：2013-03-26

    申请号：US12781780

    申请日：2010-05-17

    申请人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce D. Buch

    发明人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce D. Buch

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5642 ,  G11C2029/0411

    摘要： Methods and systems for accessing encoded data stored in a solid state non-volatile memory device include iteratively demodulating and decoding the data. The memory device includes memory cells arranged to store multiple bits of data per memory cell. The memory cells are capable of storing multiple pages of data. Each bit stored in a memory cell is associated with a page of data that is different from other pages associated with other bits stored in the memory cell. The multiple pages are demodulated responsive to sensed voltage levels of the memory cells, and a demodulated output is provided for each page of the multiple pages. A decoded output for each page of the multiple pages is generated. Decoding the page and demodulating the multiple pages proceeds iteratively, including an exchange of information between the decoder and the demodulator.

    摘要翻译： 访问存储在固态非易失性存储器件中的编码数据的方法和系统包括对数据进行迭代解调和解码。 存储器件包括存储器单元，其被布置为存储每个存储器单元的多个位数据。 存储单元能够存储多页数据。 存储在存储器单元中的每个位与与存储在存储单元中的其它位相关的其它页不同的数据页相关联。 响应于感测的存储器单元的电压电平对多页进行解调，并且为多页的每一页提供解调输出。 生成多页的每一页的解码输出。 对页面进行解码并解调多个页面进行迭代，包括解码器和解调器之间的信息交换。

    JOINT ENCODING OF LOGICAL PAGES IN MULTI-PAGE MEMORY ARCHITECTURE
    4.
    发明申请
    JOINT ENCODING OF LOGICAL PAGES IN MULTI-PAGE MEMORY ARCHITECTURE 有权
    多页存储器架构中逻辑页面的编辑

    公开(公告)号：US20110280068A1

    公开(公告)日：2011-11-17

    申请号：US12781774

    申请日：2010-05-17

    申请人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce Buch

    发明人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce Buch

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C29/00 ,  G11C2216/14

    摘要： Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of the multi-level memory cells while a second logical page of the multiple logical pages is temporarily cached. After the first logical page is stored as the first bits of the memory cell, the second logical page is stored as second bits of the memory cells.

    摘要翻译： 多个逻辑页面被联合编码成单个码字，并被存储在具有多层存储器单元的固态非易失性存储器（NVM）设备的相同物理页面中。 多个逻辑页面的第一逻辑页面被存储在存储器设备中作为多级存储器单元的第一位，而多个逻辑页面的第二逻辑页面被临时高速缓存。 在将第一逻辑页面存储为存储器单元的第一位之后，第二逻辑页面被存储为存储器单元的第二位。

    Joint encoding of logical pages in multi-page memory architecture
    5.
    发明授权
    Joint encoding of logical pages in multi-page memory architecture 有权
    在多页内存架构中对逻辑页进行联合编码

    公开(公告)号：US08254167B2

    公开(公告)日：2012-08-28

    申请号：US12781774

    申请日：2010-05-17

    申请人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce D. Buch

    发明人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce D. Buch

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C29/00 ,  G11C2216/14

    摘要： Multiple logical pages are jointly encoded into a single code word and are stored in the same physical page of a solid state non-volatile memory (NVM) device having multi-level memory cells. A first logical page of the multiple logical pages is stored in the memory device as first bits of the multi-level memory cells while a second logical page of the multiple logical pages is temporarily cached. After the first logical page is stored as the first bits of the memory cell, the second logical page is stored as second bits of the memory cells.

    摘要翻译： 多个逻辑页面被联合编码成单个码字，并被存储在具有多层存储器单元的固态非易失性存储器（NVM）设备的相同物理页面中。 多个逻辑页面的第一逻辑页面被存储在存储器设备中作为多级存储器单元的第一位，而多个逻辑页面的第二逻辑页面被临时高速缓存。 在将第一逻辑页面存储为存储器单元的第一位之后，第二逻辑页面被存储为存储器单元的第二位。

    ITERATIVE DEMODULATION AND DECODING FOR MULTI-PAGE MEMORY ARCHITECTURE
    6.
    发明申请
    ITERATIVE DEMODULATION AND DECODING FOR MULTI-PAGE MEMORY ARCHITECTURE 有权
    多媒体存储器架构的迭代解码和解码

    公开(公告)号：US20110280069A1

    公开(公告)日：2011-11-17

    申请号：US12781780

    申请日：2010-05-17

    申请人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce D. Buch

    发明人： Ara Patapoutian ,  Deepak Sridhara ,  Bruce D. Buch

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C11/5642 ,  G11C2029/0411

    摘要： Methods and systems for accessing encoded data stored in a solid state non-volatile memory device include iteratively demodulating and decoding the data. The memory device includes memory cells arranged to store multiple bits of data per memory cell. The memory cells are capable of storing multiple pages of data. Each bit stored in a memory cell is associated with a page of data that is different from other pages associated with other bits stored in the memory cell. The multiple pages are demodulated responsive to sensed voltage levels of the memory cells, and a demodulated output is provided for each page of the multiple pages. A decoded output for each page of the multiple pages is generated. Decoding the page and demodulating the multiple pages proceeds iteratively, including an exchange of information between the decoder and the demodulator.

    摘要翻译： 访问存储在固态非易失性存储器件中的编码数据的方法和系统包括对数据进行迭代解调和解码。 存储器件包括存储器单元，其被布置为存储每个存储器单元的多个位数据。 存储单元能够存储多页数据。 存储在存储器单元中的每个位与与存储在存储单元中的其它位相关的其它页不同的数据页相关联。 响应于感测的存储器单元的电压电平对多页进行解调，并且为多页的每一页提供解调输出。 生成多页的每一页的解码输出。 对页面进行解码并解调多个页面进行迭代，包括解码器和解调器之间的信息交换。

    OUTER CODE PROTECTION FOR SOLID STATE MEMORY DEVICES
    7.
    发明申请
    OUTER CODE PROTECTION FOR SOLID STATE MEMORY DEVICES 有权
    固态存储器件的外部代码保护

    公开(公告)号：US20110296272A1

    公开(公告)日：2011-12-01

    申请号：US12790120

    申请日：2010-05-28

    申请人： Bernardo Rub ,  Ara Patapoutian ,  Arvind Sridharan ,  Bruce D. Buch

    发明人： Bernardo Rub ,  Ara Patapoutian ,  Arvind Sridharan ,  Bruce D. Buch

    IPC分类号： H03M13/29 ,  G06F11/10

    CPC分类号： G06F11/1012

    摘要： Outer code words can span multiple data blocks, multiple die, or multiple chips of a memory device to protect against errors in the data stored in the blocks, die and/or chips. A solid state memory device is arranged in multiple data blocks, each block including an array of memory cells arranged in a plurality of pages. The data is encoded into inner code words and symbol-based outer code words. The inner code words and the symbol-based outer code words are stored in the memory cells of the multiple blocks. One or more inner code words are stored in each page of each block and one or more symbols of each outer code word are stored in at least one page of each block. The inner code words and the outer code words are read from the memory device and are used to correct the errors in the data.

    摘要翻译： 外码字可以跨越存储器设备的多个数据块，多个芯片或多个芯片，以防止存储在块，芯片和/或芯片中的数据中的错误。 固态存储器件被布置在多个数据块中，每个块包括以多页布置的存储器单元的阵列。 数据被编码成内码字和基于符号的外码字。 内码字和基于符号的外码字被存储在多个块的存储单元中。 一个或多个内部码字被存储在每个块的每个页面中，并且每个外部码字的一个或多个符号被存储在每个块的至少一个页面中。 内部码字和外部码字从存储器件读取并用于校正数据中的错误。

    Group based codes for multi-dimensional recording (MDR)
    8.
    发明授权
    Group based codes for multi-dimensional recording (MDR) 有权
    用于多维记录（MDR）的基于组的代码

    公开(公告)号：US09396062B1

    公开(公告)日：2016-07-19

    申请号：US14245886

    申请日：2014-04-04

    申请人： Deepak Sridhara ,  William Radich ,  Ara Patapoutian ,  Timothy R Feldman ,  Mark Gaertner

    发明人： Deepak Sridhara ,  William Radich ,  Ara Patapoutian ,  Timothy R Feldman ,  Mark Gaertner

    IPC分类号： G11C29/00 ,  G06F11/10

    CPC分类号： G06F11/1044 ,  G06F11/1008 ,  G06F11/1068

    摘要： A multi-dimensional recording (MDR) system may include a group based coding circuit (GBCC) which can implement error correcting codes via outer codes. The GBCC can implement outer codes, including interleaving outer codes, in MDR systems where inner codewords include multiple memory groupings. The multiple memory groupings may be across different structural divisions within a data storage medium; or could be across multiple different data storage mediums.

    摘要翻译： 多维记录（MDR）系统可以包括基于组的编码电路（GBCC），其可以通过外部代码实现纠错码。 GBCC可以在其中内部码字包括多个存储器分组的MDR系统中实现外部代码，包括交织外部代码。 多个存储器分组可以跨数据存储介质中的不同结构划分; 或者可以跨越多个不同的数据存储介质。

    DETERMINATION OF MEMORY READ REFERENCE AND PROGRAMMING VOLTAGES
    9.
    发明申请
    DETERMINATION OF MEMORY READ REFERENCE AND PROGRAMMING VOLTAGES 有权
    记忆读取参考和编程电压的确定

    公开(公告)号：US20130094289A1

    公开(公告)日：2013-04-18

    申请号：US13275497

    申请日：2011-10-18

    申请人： Arvind Sridharan ,  Ara Patapoutian

    发明人： Arvind Sridharan ,  Ara Patapoutian

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/28 ,  G11C16/3418

    摘要： Symmetrical or asymmetrical noise distributions for voltages corresponding to symbols that can be stored in multi-level memory cells (MLCs) of a memory device are used to determine read reference and/or programming voltages. The read reference voltages and/or programming voltages for the MLCs are jointly determined using the symmetrical distributions and a maximum likelihood estimation (MLE) and/or by determining at least one of the read reference voltages and the programming voltages using the asymmetrical distributions.

    摘要翻译： 用于对应于可存储在存储器件的多级存储器单元（MLC）中的符号的电压的对称或非对称噪声分布用于确定读取参考和/或编程电压。 使用对称分布和最大似然估计（MLE）和/或通过使用不对称分布确定读取的参考电压和编程电压中的至少一个来共同确定MLC的读取参考电压和/或编程电压。

    DETERMINING OPTIMAL READ REFERENCE AND PROGRAMMING VOLTAGES FOR NON-VOLATILE MEMORY USING MUTUAL INFORMATION
    10.
    发明申请
    DETERMINING OPTIMAL READ REFERENCE AND PROGRAMMING VOLTAGES FOR NON-VOLATILE MEMORY USING MUTUAL INFORMATION 失效
    使用相关信息确定非易失性存储器的最佳读取参考和编程电压

    公开(公告)号：US20130094286A1

    公开(公告)日：2013-04-18

    申请号：US13275598

    申请日：2011-10-18

    申请人： Arvind Sridharan ,  Ara Patapoutian

    发明人： Arvind Sridharan ,  Ara Patapoutian

    IPC分类号： G11C16/10

    CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3418

    摘要： Approaches for operating a memory device comprising memory cells are disclosed. Optimal values for one or more of programming voltages used to program memory cells of the memory device and read reference voltages used to read the memory cells are determined using a mutual information function, I(X; Y), where X represents data values programmed to the memory cells and Y represents data values read from the memory cells. The read reference and/or programming voltages used for reading and/or programming the memory cells are adjusted using the optimal values.

    摘要翻译： 公开了用于操作包括存储器单元的存储器件的方法。 使用用于对存储器件的存储器单元编程的一个或多个编程电压和用于读取存储器单元的读取参考电压的最佳值使用互信息函数I（X; Y）确定，其中X表示被编程为 存储单元，Y表示从存储器单元读取的数据值。 用于读取和/或编程存储器单元的读取参考和/或编程电压使用最佳值进行调整。