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公开(公告)号：US4616310A
公开(公告)日：1986-10-07
申请号：US496726
申请日：1983-05-20
CPC分类号： G06F15/167 , G06F12/0813
摘要： A communicating random access shared memory configuration for a multiprocessor system is connected to the processors for transferring data between the processors. The random access memory configuration includes a plurality of interconnected random access memory chips, each of these memory chips including first and second separate memory bit arrays having N word storage locations of M bit length with M bit buffer connected in between the first and second bit arrays on each memory chip, and first and second input/output ports connected to first and second bit arrays on each chip for entering and removing data externally to and from the chip. A controller is located on each chip and connected to the first and second memory arrays and the M bit buffer for transferring data between the first and second memory arrays and into and out of the first and second input/output ports.
摘要翻译： 用于多处理器系统的通信随机存取共享存储器配置被连接到处理器以在处理器之间传送数据。 随机存取存储器配置包括多个互连的随机存取存储器芯片，这些存储器芯片中的每一个包括第一和第二分离存储器位阵列，其具有M位长度的N字存储位置，M位缓冲器连接在第一和第二位阵列之间 在每个存储器芯片上，以及连接到每个芯片上的第一和第二位阵列的第一和第二输入/输出端口，用于从芯片外部输入和从芯片移除数据。 控制器位于每个芯片上并且连接到第一和第二存储器阵列以及M位缓冲器，用于在第一和第二存储器阵列之间传送数据并进入和离开第一和第二输入/输出端口。
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2.发明授权Circuits for accessing a variable width data bus with a variable width data field 失效用于使用可变宽度数据字段访问可变宽度数据总线的电路
公开(公告)号：US4667305A
公开(公告)日：1987-05-19
申请号：US394044
申请日：1982-06-30
CPC分类号： G06F7/764 , G06F13/4018 , G06F5/00 , G06F5/01
摘要： A general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width N.sub.c and a data field of N.sub.f, the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field N.sub.f extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at position 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus. The structure includes a modulo N.sub.c combinational ring shifter for aligning the data field with the data bus. An overflow signal generator is provided using a subtraction circuit wherein the data field width is subtracted from the data bus width between alignment bit n and the end bit N.sub.c. A negative subtraction result indicates overflow and the magnitude of the result specifies the bit positions from bit 1 of the data bus for the wrapped around bits. A select signal generator including two decoders is provided to indicate the valid data bit positions of the data bus.
摘要翻译： 一种用于并行访问可变宽度数据总线的通用位操纵器结构，其中，利用可变宽度Nc的数据总线和Nf的数据字段，结构可以将数据字段放置在数据总线上，数据字段的位1与 数据总线宽度内的选定位n。 如果数据字段Nf扩展到数据总线的末尾，则数据字段的溢出位将被“缠绕”并放置在从数据总线的位置1开始的数据总线的开头处。 此外，产生特殊信号并伴随这些溢出或包装位。 此外，当数据字段的宽度小于数据总线的宽度时，生成选择信号以指示数据总线的哪些位包含有效数据。 该结构包括用于将数据场与数据总线对准的模Nc组合移相器。 使用减法电路提供溢出信号发生器，其中数据字段宽度从对准位n和结束位Nc之间的数据总线宽度减去。 负减法结果表示溢出，结果的大小指定了数据总线的位1的位位置。 提供包括两个解码器的选择信号发生器以指示数据总线的有效数据位位置。
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公开(公告)号：US06564274B1
公开(公告)日：2003-05-13
申请号：US09466463
申请日：1999-12-17
IPC分类号： G06F1342
CPC分类号： G06F13/40
摘要： In concentrated multiprocessor systems conforming to the presently disclosed modular architecture, a host processor and plural client processors are packaged in a single box containing a high speed (short length) bus connecting all of the processors, and data storage resources via the bus. The bus may be of a type commonly used in contemporary single computer systems; e.g. one conforming to PCI specifications. The host processor and associated resources are mounted directly on an integrated circuit motherboard containing the bus and card connectors attached to the bus. The card connectors removably receive integrated circuit cards containing individual client processors. In one embodiment, client processors are configured to be used as workstations or PC's—in a residence, office or small factory environment—relative to users and accessories remote from the system enclosure. In another embodiment, host and client processors are configured to operate as servers between the system and multiple data networks external to the system; the host and client subsystems thereby constituting a server “farm”.
摘要翻译： 在符合目前公开的模块化架构的集中多处理器系统中，主处理器和多个客户端处理器被封装在包含连接所有处理器的高速（短长度）总线的单个盒中，以及经由总线的数据存储资源。 公共汽车可能是当代单台计算机系统中常用的类型; 例如 一个符合PCI规范。 主处理器和相关资源直接安装在集成电路主板上，该集成电路板包含连接到总线的总线和卡连接器。 卡连接器可拆卸地接收包含单个客户端处理器的集成电路卡。 在一个实施例中，相对于远离系统机箱的用户和附件，客户端处理器被配置为用作驻留，办公室或小型工厂环境中的工作站或PC。 在另一个实施例中，主机和客户端处理器被配置为作为系统与系统外部的多个数据网络之间的服务器进行操作; 主机和客户端子系统由此构成服务器“farm”。
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