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公开(公告)号：US4714994A
公开(公告)日：1987-12-22
申请号：US728724
申请日：1985-04-30
IPC分类号： G06F9/38
CPC分类号： G06F9/381 , G06F9/3802
摘要： An instruction prefetch buffer control (20) is provided for an instruction prefetch buffer array (10) which stores the code for a number of instructions that have already been executed as well as the code for a number of instructions yet to be executed. The instruction prefetch buffer control includes a register (201) for storing an instruction fetch pointer, this pointer being supplied to the buffer array (10) as a write pointer which points to the location in the array where a new word is to be written from main memory. A second register (205) stores an instruction execution pointer which is supplied to the buffer array (10) as a read pointer. A first adder (203) increments the first register to increment the instruction fetch pointer for sequential instructions and calculates a new instruction fetch pointer for branch instructions. A second adder (215) increments the second register to increment the instruction execution pointer for sequential instructions and calculates a new instruction execution pointer for branch instructions. Incrementing of the second register is variable depending on the length of the instruction. A third adder ( 221) is responsive to the output of the first adder and a branch target address to calculate whether the target instruction is contained in the array (10) and, if it is, causes the new instruction execution pointer calculated by the second adder (215) to be loaded into the second register (205).
摘要翻译： 为指令预取缓冲器阵列（10）提供指令预取缓冲器控制（20），该指令预取缓冲器阵列（10）存储已经执行的多个指令的代码以及尚待执行的多个指令的代码。 指令预取缓冲器控制包括用于存储指令提取指针的寄存器（201），该指针作为写入指针提供给缓冲器阵列（10），该指针指向阵列中要写入新单词的位置， 主记忆 第二寄存器（205）存储作为读指针提供给缓冲器阵列（10）的指令执行指针。 第一加法器（203）递增第一寄存器以递增用于顺序指令的指令获取指针，并计算用于转移指令的新指令取指针。 第二加法器（215）递增第二寄存器以递增用于顺序指令的指令执行指针，并计算分支指令的新指令执行指针。 根据指令的长度，第二个寄存器的递增是可变的。 第三加法器（221）响应于第一加法器的输出和分支目标地址来计算目标指令是否包含在数组（10）中，并且如果是，则使得由第二加法器计算的新指令执行指针 加法器（215）被加载到第二寄存器（205）中。
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公开(公告)号：US07012607B1
公开(公告)日：2006-03-14
申请号：US09437560
申请日：1999-11-10
申请人： David J. Kurlander , Daniel T. Ling
发明人： David J. Kurlander , Daniel T. Ling
CPC分类号： G06F9/45512 , G06F9/451 , G06F2209/545 , Y10S345/949 , Y10S345/952 , Y10S345/96
摘要： A system and/or method that generates user interface output sequences controlled by a user interface output system. The user interface output system can provide event definitions to an application pro that specify high-level actions to be performed by the sequence and can issue low-level commands to direct the actions of the user interface output sequence. The user interface output system provides a user interface output controller, which acts as an interface between an application program and the low-level commands which specify tasks for the user interface output sequence to perform. The user interface output controller is generated from a specification, using a planning methodology.
摘要翻译： 一种生成由用户界面输出系统控制的用户界面输出序列的系统和/或方法。 用户界面输出系统可以向指定要由序列执行的高级动作的应用程序提供事件定义，并且可以发出低级命令以指导用户界面输出序列的动作。 用户界面输出系统提供用户界面输出控制器，用作应用程序与指定用户界面输出序列执行任务的低级命令之间的接口。 用户界面输出控制器是根据规范生成的，使用规划方法。
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公开(公告)号：US4541075A
公开(公告)日：1985-09-10
申请号：US393996
申请日：1982-06-30
IPC分类号： G11C11/41 , G09G5/39 , G11C7/00 , G11C7/10 , G11C8/16 , G11C11/401 , G11C11/406 , G11C11/40
CPC分类号： G11C11/406 , G09G5/39 , G11C7/1075 , G11C8/16 , G09G2360/126
摘要： A semiconductor random access memory is provided having a second asynchronous input/output port. Block transfers of data can be effected to and from the memory using the second input/output port. Memory throughput efficiency is improved permitting functions such as display refresh in a mapped memory display to be accomplished through the second input/output port. Memory bus contention on the primary port is also relieved. The main input/output port is thereby free to receive new data for a higher percentage of available transfer time since refresh data is available at the second input/output port.
摘要翻译： 提供具有第二异步输入/输出端口的半导体随机存取存储器。 可以使用第二输入/输出端口对存储器进行数据的块传输。 改进了存储器吞吐量效率，允许通过第二输入/输出端口实现映射存储器显示中的显示刷新等功能。 主端口上的内存总线争用也得到缓解。 由于刷新数据在第二输入/输出端口可用时，主输入/输出端口可以自由地接收新的可用传输时间百分比的新数据。
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公开(公告)号：US4700086A
公开(公告)日：1987-10-13
申请号：US726211
申请日：1985-04-23
IPC分类号： H03K19/096 , H03K17/687 , H03K19/173 , H03K19/003
CPC分类号： H03K19/1738
摘要： A precharge circuit for a cascode voltage switch in which at the beginning of the precharge phase the output state is memorized and the output is isolated from the precharging points. Both the positive and negative ends of the discharge paths are precharged with the gates of the switches in all paths held in their memorized states. Towards the end of precharging, the output is reconnected to the normal precharging point so that it goes low. Then the positive and negative precharging points are reconnected for their evaluation configuration.
摘要翻译： 一种用于共源共栅电压开关的预充电电路，其中在预充电阶段开始时，存储输出状态并且输出与预充电点隔离。 放电路径的正端和负端均在保持在其存储状态的所有路径中的开关的栅极预充电。 在预充电结束时，输出将重新连接到正常的预充电点，使其变低。 然后将正，负预充电点重新连接起来进行评估。
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5.发明授权Circuits for accessing a variable width data bus with a variable width data field 失效用于使用可变宽度数据字段访问可变宽度数据总线的电路
公开(公告)号：US4667305A
公开(公告)日：1987-05-19
申请号：US394044
申请日：1982-06-30
CPC分类号： G06F7/764 , G06F13/4018 , G06F5/00 , G06F5/01
摘要： A general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width N.sub.c and a data field of N.sub.f, the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field N.sub.f extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at position 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus. The structure includes a modulo N.sub.c combinational ring shifter for aligning the data field with the data bus. An overflow signal generator is provided using a subtraction circuit wherein the data field width is subtracted from the data bus width between alignment bit n and the end bit N.sub.c. A negative subtraction result indicates overflow and the magnitude of the result specifies the bit positions from bit 1 of the data bus for the wrapped around bits. A select signal generator including two decoders is provided to indicate the valid data bit positions of the data bus.
摘要翻译： 一种用于并行访问可变宽度数据总线的通用位操纵器结构，其中，利用可变宽度Nc的数据总线和Nf的数据字段，结构可以将数据字段放置在数据总线上，数据字段的位1与 数据总线宽度内的选定位n。 如果数据字段Nf扩展到数据总线的末尾，则数据字段的溢出位将被“缠绕”并放置在从数据总线的位置1开始的数据总线的开头处。 此外，产生特殊信号并伴随这些溢出或包装位。 此外，当数据字段的宽度小于数据总线的宽度时，生成选择信号以指示数据总线的哪些位包含有效数据。 该结构包括用于将数据场与数据总线对准的模Nc组合移相器。 使用减法电路提供溢出信号发生器，其中数据字段宽度从对准位n和结束位Nc之间的数据总线宽度减去。 负减法结果表示溢出，结果的大小指定了数据总线的位1的位位置。 提供包括两个解码器的选择信号发生器以指示数据总线的有效数据位位置。
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公开(公告)号：US4663729A
公开(公告)日：1987-05-05
申请号：US616047
申请日：1984-06-01
摘要： A display architecture is disclosed which supports a variable, selectable number of bits per chip and a variable, selectable segment width. The architecture comprises a plurality of dynamic memory chips and a function generator. Each of the memory chips includes at least two data islands wherein each data island has its own data in/out line, chip select and increment bit supplied by the function generator. The function generator receives a starting address X.sub.o, Y.sub.o, the data path width N.sub.D and an encoded segment width S. A bit incrementer in the function generator generates increment bits A.sub.I based on the externally supplied modulo N.sub.D. The function generator generates the physical word address w.sub.o and physical bit address b.sub.o based on the starting address X.sub.o, Y.sub.o, the data path width N.sub.D and the encoded segment width S. Logic circuitry is provided which is responsive to an overflow bit produced by the bit incrementer to control spill and wrap functions. Spill results from the usual bit address incrementing where the data spills from the highest order chip to the lowest. Wrap is a special case when spill occurs at the right hand edge of the screen and data wraps around on the same scan line to the left hand edge of the screen.
摘要翻译： 公开了一种显示架构，其支持每个芯片的可变的，可选择的位数和可变的可选择的段宽度。 该架构包括多个动态存储器芯片和功能发生器。 每个存储器芯片包括至少两个数据岛，其中每个数据岛具有其自身的数据输入/输出，由功能发生器提供的片选和递增位。 函数发生器接收起始地址Xo，Yo，数据路径宽度ND和编码段宽度S.函数发生器中的位增量器基于外部提供的模ND产生增量位AI。 函数发生器基于起始地址Xo，Yo，数据路径宽度ND和编码段宽度S生成物理字地址wo和物理位地址bo。提供响应于由位产生的溢出位的逻辑电路 增量器来控制溢出和包装功能。 从数据溢出从最高订单芯片到最低位的通常的位地址递增溢出结果。 包装是在屏幕右侧边缘发生溢出的特殊情况，并且数据在同一扫描线周围卷绕到屏幕的左侧边缘。
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公开(公告)号：US4649516A
公开(公告)日：1987-03-10
申请号：US616045
申请日：1984-06-01
申请人： Paul W. Chung , Richard E. Matick , Daniel T. Ling
发明人： Paul W. Chung , Richard E. Matick , Daniel T. Ling
IPC分类号： G11C11/401 , G06F12/00 , G11C7/10 , G11C11/4093 , G06F13/38
CPC分类号： G11C7/106 , G11C11/4093 , G11C7/1051 , G11C7/1075
摘要： A dynamic row buffer circuit is disclosed for a dynamic random access memory (DRAM) chip which enables the DRAM chip to be used for special function applications. The dynamic row buffer comprises a row buffer master register and a row buffer slave register. The row buffer master register comprises a plurality of master circuits (M1) and a plurality of slave circuits (S1). Likewise, the row buffer slave register comprises a plurality of master circuits (M2) and a plurality of slave circuits (S2). The row buffer master register is parallel load and parallel read-out with the outputs of the master register slave circuits being connected to the master circuits of the slave register. The row buffer slave register is a parallel load, serial read-out register with the output being shifted out of a secondary output port. The entire row buffer can be isolated from the memory array, and when so isolated, the memory array can be accessed through the primary input/output port in the same way as in an ordinary DRAM chip. This arrangement permits the conversion of a DRAM chip to a dual port display, of which a specific example is disclosed, or some other special function RAM thereby adding a large value to the DRAM chip with little additional cost.
摘要翻译： 公开了用于动态随机存取存储器（DRAM）芯片的动态行缓冲器电路，其使DRAM芯片能够用于特殊功能应用。 动态行缓冲器包括行缓冲器主寄存器和行缓冲器从寄存器。 行缓冲器主寄存器包括多个主电路（M1）和多个从电路（S1）。 类似地，行缓冲器从机寄存器包括多个主电路（M2）和多个从电路（S2）。 行缓冲器主寄存器是并行负载并行读出，主寄存器从电路的输出端连接到从机寄存器的主电路。 行缓冲器从寄存器是一个并行负载，串行读出寄存器，输出端从辅助输出端口移出。 整个行缓冲器可以与存储器阵列隔离，并且当这样隔离时，存储器阵列可以以与普通DRAM芯片相同的方式通过主输入/输出端口访问。 这种布置允许将DRAM芯片转换为双端口显示器，其中公开了一个具体示例，或者一些其他特殊功能RAM，从而以少量额外成本为DRAM芯片增加了大的价值。
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公开(公告)号：US4616310A
公开(公告)日：1986-10-07
申请号：US496726
申请日：1983-05-20
CPC分类号： G06F15/167 , G06F12/0813
摘要： A communicating random access shared memory configuration for a multiprocessor system is connected to the processors for transferring data between the processors. The random access memory configuration includes a plurality of interconnected random access memory chips, each of these memory chips including first and second separate memory bit arrays having N word storage locations of M bit length with M bit buffer connected in between the first and second bit arrays on each memory chip, and first and second input/output ports connected to first and second bit arrays on each chip for entering and removing data externally to and from the chip. A controller is located on each chip and connected to the first and second memory arrays and the M bit buffer for transferring data between the first and second memory arrays and into and out of the first and second input/output ports.
摘要翻译： 用于多处理器系统的通信随机存取共享存储器配置被连接到处理器以在处理器之间传送数据。 随机存取存储器配置包括多个互连的随机存取存储器芯片，这些存储器芯片中的每一个包括第一和第二分离存储器位阵列，其具有M位长度的N字存储位置，M位缓冲器连接在第一和第二位阵列之间 在每个存储器芯片上，以及连接到每个芯片上的第一和第二位阵列的第一和第二输入/输出端口，用于从芯片外部输入和从芯片移除数据。 控制器位于每个芯片上并且连接到第一和第二存储器阵列以及M位缓冲器，用于在第一和第二存储器阵列之间传送数据并进入和离开第一和第二输入/输出端口。
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公开(公告)号：US4577293A
公开(公告)日：1986-03-18
申请号：US616046
申请日：1984-06-01
申请人： Richard E. Matick , Daniel T. Ling
发明人： Richard E. Matick , Daniel T. Ling
CPC分类号： G06F12/0893 , G06F12/0864 , G06F12/1063 , G11C7/1075 , G11C8/12
摘要： The cache reload time in small computer systems is improved by using a distributed cache located on the memory chips. The large bandwidth between the main memory and cache is the usual on-chip interconnecting lines which avoids pin input/output problems. This distributed cache is achieved by the use of communicating random access memory chips of the type incorporating a primary port (10) and a secondary port (14). Ideally, the primary and secondary ports can run totally independently of each other. The primary port functions as in a typical dynamic random access memory and is the usual input/output path for the memory chips. The secondary port, which provides the distributed cache, makes use of a separate master/slave row buffer (15) which is normally isolated from the sense amplifier/latches. Once this master/slave row buffer is loaded, it can be accessed very fast, and the large bandwidth between the main memory array and the on-chip row buffer provides a very fast reload time for a cache miss.
摘要翻译： 通过使用位于存储器芯片上的分布式缓存来提高小型计算机系统中的缓存重新加载时间。 主存储器和高速缓存之间的大带宽是通常的片上互连线，避免了引脚输入/输出问题。 通过使用包含主端口（10）和辅助端口（14）的类型的通信随机存取存储器芯片来实现该分布式高速缓存。 理想情况下，主端口和辅助端口可以完全独立运行。 主端口在典型的动态随机存取存储器中起作用，并且是用于存储器芯片的通常的输入/输出路径。 提供分布式缓存的辅助端口使用通常与读出放大器/锁存器隔离的单独的主/从行行缓冲器（15）。 一旦这个主/从行缓冲器被加载，它可以非常快速地访问，并且主存储器阵列和片上行缓冲器之间的大带宽为缓存未命中提供非常快的重新加载时间。
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