公开(公告)号：US08015341B2

公开(公告)日：2011-09-06

申请号：US10592190

申请日：2005-03-21

申请人： David R. Evoy ,  Dc Sessions ,  Dennis Koutsoures

发明人： David R. Evoy ,  Dc Sessions ,  Dennis Koutsoures

IPC分类号： G06F13/20

CPC分类号： G06F13/4072

摘要： A communications port is implemented for configuration in direction and arrangement. According to an example embodiment of the present invention, a communications link (110), such as a PCI Express type link, is configurable for communicating with devices having different directional and/or polarity configurations. The communications link is configured to match a communications port condition (e.g., a directional and/or polarity condition) of a device (120) coupled to the communications link. In one instance, the communications link is directionally configurable for reassigning input lanes to output lanes and output lanes to input lanes. With this approach, the communications link can be used to communicate with a variety of devices having varied communication characteristics.

摘要翻译： 实现通信端口用于配置方向和布置。 根据本发明的示例性实施例，诸如PCI Express类型链路的通信链路（110）可配置为与具有不同方向和/或极性配置的设备进行通信。 通信链路被配置为匹配耦合到通信链路的设备（120）的通信端口条件（例如，定向和/或极性条件）。 在一种情况下，通信链路是可定向配置的，用于重新分配输入通道以输出通道和输出通道到输入通道。 利用这种方法，通信链路可用于与具有不同通信特性的各种设备进行通信。

公开(公告)号：US06457075B1

公开(公告)日：2002-09-24

申请号：US09313244

申请日：1999-05-17

申请人： Dennis Koutsoures

发明人： Dennis Koutsoures

IPC分类号： G06F1328

CPC分类号： G06F13/28

摘要： A computer system with a multi-master system bus includes a memory controller that changes the burst mode of the including memory system automatically as a function of the selected master. The controller includes a programmable look-up table into which is stored a value B corresponding to a fixed memory burst mode; for each master, a multiplier is stored indicating the multiple of the burst mode that would be optimal for that master. The grant signal used to select the current master is also used to select the multiplier M associated with that master. In response to a read request by the current master, a requested address is forwarded to the memory. Then the controller generates and transmits M−1 addresses spaced B addresses apart every Bth bus cycle. This implements a memory system burst of M*B addresses with no latencies between successive B-address memory bursts. The memory system burst can be aborted if an address in the burst is not confirmed by a subsequent address request by the master. This approach improves the performance of a multi-master system by avoiding latencies normally involved in changing burst modes when a switch is made between masters having different burst mode requirements. The approach is preferable to utilizing long bursts that must be aborted frequently. Typically, when a write operation follows a burst, the burst is terminated upon completion—avoiding latencies involved in clearing an aborted burst before a write operation can be executed.

摘要翻译： 具有多主系统总线的计算机系统包括存储器控制器，其根据所选主机自动地改变包括存储器系统的突发模式。 控制器包括可编程查询表，其中存储有对应于固定存储器突发模式的值B; 对于每个主机，存储一个乘法器，指示对于该主机是最佳的突发模式的倍数。 用于选择当前主机的授权信号也用于选择与该主机相关联的乘法器M. 响应于当前主机的读请求，请求的地址被转发到存储器。 然后控制器产生并发送每B个总线周期间隔B个地址的M-1地址。 这实现了在连续B地址存储器突发之间没有延迟的M * B地址的存储器系统突发。 如果突发中的地址未被主机的后续地址请求确认，则可以中止存储器系统突发。 这种方法通过避免在具有不同突发模式要求的主机之间进行切换时改变突发模式时通常涉及的延迟，来提高多主系统的性能。 该方法优于使用必须频繁中止的长脉冲串。 通常，当写入操作遵循突发时，突发在完成时终止 - 避免在执行写入操作之前清除中止的突发所涉及的延迟。

公开(公告)号：US08022727B2

公开(公告)日：2011-09-20

申请号：US12864241

申请日：2009-01-27

申请人： Dennis Koutsoures

发明人： Dennis Koutsoures

IPC分类号： H03K19/0175

CPC分类号： H03K19/1731

摘要： An electronic clamp is provided for an integrated circuit having a first voltage island (1) to which an output signal (clamp out) of the clamp is applied and a second voltage island (2) operative to produce an input signal (clamp in) to the clamp, where power to the second voltage island can be switched off to save power. The clamp comprises a latch (22) which stores or retains the clamp value (0 or 1) of the input signal (clamp in) during a reset period and clamps the output signal (clamp out) to the stored or retained value in response to a clamp enable signal, (clamp in) in order to protect the first voltage island from a non-stabilised input signal.

摘要翻译： 提供一种用于集成电路的电子夹具，该集成电路具有施加夹具的输出信号（钳位）的第一电压岛（1）和用于产生输入信号（夹入）的第二电压岛 夹具可以关闭第二电压岛的电源，以节省电力。 夹具包括在复位期间存储或保持输入信号（钳位）的钳位值（0或1）的锁存器（22），并将输出信号（钳位）钳位到存储或保留的值，以响应于 钳位使能信号（钳位），以便保护第一电压岛免受非稳定输入信号的影响。

公开(公告)号：US20090043931A1

公开(公告)日：2009-02-12

申请号：US10592190

申请日：2005-03-21

申请人： David R. Evoy ,  Dc Sessions ,  Dennis Koutsoures

发明人： David R. Evoy ,  Dc Sessions ,  Dennis Koutsoures

IPC分类号： G06F13/00 ,  G06F13/20

CPC分类号： G06F13/4072

摘要： A communications port is implemented for configuration in direction and arrangement. According to an example embodiment of the present invention, a communications link, such as a PCI Express type link, is configurable for communicating with devices having different directional and/or polarity configurations. The communications link is configured to match a communications port condition (e.g., a directional and/or polarity condition) of a device coupled to the communications link. In one instance, the communications link is directionally configurable for reassigning input lanes to output lanes and output lanes to input lanes. With this approach, the communications link can be used to communicate with a variety of devices having varied communication characteristics.

摘要翻译： 实现通信端口用于配置方向和布置。 根据本发明的示例性实施例，诸如PCI Express类型链路的通信链路可配置为与具有不同方向和/或极性配置的设备进行通信。 通信链路被配置为匹配耦合到通信链路的设备的通信端口条件（例如，定向和/或极性条件）。 在一种情况下，通信链路是可定向配置的，用于重新分配输入通道以输出通道和输出通道到输入通道。 利用这种方法，通信链路可用于与具有不同通信特性的各种设备进行通信。

公开(公告)号：US08437277B2

公开(公告)日：2013-05-07

申请号：US12734009

申请日：2008-10-03

申请人： Andrei Radulescu ,  Dennis Koutsoures ,  Peter Van Den Hamer

发明人： Andrei Radulescu ,  Dennis Koutsoures ,  Peter Van Den Hamer

IPC分类号： H04L12/28

CPC分类号： H04L61/2038 ,  H04L29/12254

摘要： Disclosed are methods, and control devices (110, 210, 310) having programmable processors configured to implement methods, of communicating with a network (100, 300) having an initially unknown topology and a plurality of unknown devices. The methods use set and get configuration commands to discover the unknown devices on the network using one or more host ports of the control device, enumerating the discovered devices by using the one or more host ports to assign a different network address to each discovered device, so that the enumerated devices correspond to the network topology.

摘要翻译： 公开了具有被配置为实现与具有最初未知拓扑的网络（100,300）和多个未知设备进行通信的方法的可编程处理器的方法和控制设备（110,210,310）。 该方法使用set和get配置命令使用控制设备的一个或多个主机端口发现网络上的未知设备，通过使用一个或多个主机端口为发现的每个设备分配不同的网络地址来枚举所发现的设备， 使得枚举的设备对应于网络拓扑。

公开(公告)号：US20110044205A1

公开(公告)日：2011-02-24

申请号：US12734009

申请日：2008-10-03

申请人： Andrei Radulescu ,  Dennis Koutsoures ,  Peter Van Den Hamer

发明人： Andrei Radulescu ,  Dennis Koutsoures ,  Peter Van Den Hamer

IPC分类号： H04L12/28

CPC分类号： H04L61/2038 ,  H04L29/12254

摘要： Disclosed are methods, and control devices (110, 210, 310) having programmable processors configured to implement methods, of communicating with a network (100, 300) having an initially unknown commands to discover the unknown devices on the network using one or more host ports of the control device, enumerating the discovered devices by using the one or more host ports to assign a different network address to each discovered device, so that the enumerated devices correspond to the network topology.

摘要翻译： 公开了具有被配置为实现方法的可编程处理器的控制设备（110,210,310），其与具有最初未知命令的网络（100,300）进行通信，以使用一个或多个主机来发现网络上的未知设备 控制设备的端口，通过使用一个或多个主机端口为每个发现的设备分配不同的网络地址来枚举所发现的设备，使得所枚举的设备对应于网络拓扑。

公开(公告)号：US20100295595A1

公开(公告)日：2010-11-25

申请号：US12864241

申请日：2009-01-27

申请人： Dennis Koutsoures

发明人： Dennis Koutsoures

IPC分类号： H03K5/08 ,  H03L5/00

CPC分类号： H03K19/1731

摘要： An electronic clamp is provided for an integrated circuit having a first voltage island (1) to which an output signal (clamp out) of the clamp is applied and a second voltage island (2) operative to produce an input signal (clamp in) to the clamp, where power to the second voltage island can be switched off to save power. The clamp comprises a latch (22) which stores or retains the clamp value (0 or 1) of the input signal (clamp in) during a reset period and clamps the output signal (clamp out) to the stored or retained value in response to a clamp enable signal, (clamp in) in order to protect the first voltage island from a non-stabilised input signal.

摘要翻译： 提供一种用于集成电路的电子夹具，该集成电路具有施加夹具的输出信号（钳位）的第一电压岛（1）和用于产生输入信号（夹入）的第二电压岛 夹具可以关闭第二电压岛的电源，以节省电力。 夹具包括在复位期间存储或保持输入信号（钳位）的钳位值（0或1）的锁存器（22），并将输出信号（钳位）钳位到存储或保留的值，以响应于 钳位使能信号（钳位），以便保护第一电压岛免受非稳定输入信号的影响。

公开(公告)号：US20090323728A1

公开(公告)日：2009-12-31

申请号：US12306907

申请日：2007-06-21

申请人： Dennis Koutsoures ,  Ivan Svestka

发明人： Dennis Koutsoures ,  Ivan Svestka

IPC分类号： H04J3/06 ,  G06F12/00

CPC分类号： H04L49/901 ,  G06F5/12 ,  G06F2205/102 ,  H04L7/02 ,  H04L47/30 ,  H04L49/90

摘要： An asynchronous FIFO is provided that determines whether its buffer is primed with at least one data element during a data transfer across clock domains in order to eliminate metastability issues that cause data stalls and interruptions in data flow.

摘要翻译： 提供了异步FIFO，其在跨时钟域的数据传输期间确定其缓冲器是否被至少一个数据元素引用，以消除导致数据流失和数据流中断的亚稳态问题。

公开(公告)号：US06529424B2

公开(公告)日：2003-03-04

申请号：US09858545

申请日：2001-05-17

申请人： Dennis Koutsoures

发明人： Dennis Koutsoures

IPC分类号： G11C700

CPC分类号： G11C11/4093 ,  G06F13/1689 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  Y02D10/14

摘要： A method of indicating data availability is disclosed. According to the method a data read operation is commenced for retrieving data signals based on data stored within an SDRAM. The data is provided from the SDRAM device with a first propagation delay. The SDRAM device also provides a strobe signal having a propagation delay similar to the first propagation delay. Based on the strobe signal data is latched out of the SDRAM device, as it is available to be read.

摘要翻译： 公开了一种指示数据可用性的方法。 根据该方法，基于存储在SDRAM内的数据开始数据读取操作以检索数据信号。 数据由SDRAM器件提供，具有第一传播延迟。 SDRAM器件还提供具有类似于第一传播延迟的传播延迟的选通信号。 基于选通信号，数据从SDRAM器件被锁存，因为它可以被读取。