公开(公告)号：US08531196B1

公开(公告)日：2013-09-10

申请号：US12365147

申请日：2009-02-03

申请人： Jaydev Amit Shelat ,  Zunhang Yu Kasnavi ,  Dhananjay Srinivasa Raghavan

发明人： Jaydev Amit Shelat ,  Zunhang Yu Kasnavi ,  Dhananjay Srinivasa Raghavan

IPC分类号： G01R31/3187 ,  G01R31/26 ,  G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/2831 ,  G01R31/31725

摘要： Programmable delay test circuitry is provided for testing a circuit under test on an integrated circuit. Delay test circuitry may use logic circuitry to output an error signal when a delay time provided by the circuit under test is greater than a characteristic time that may be programmed into the programmable delay test circuitry. Programmable delay test circuitry may use a logic gate to provide a pulse that has a pulse width equal to the delay of the delay circuitry. Programmable delay test circuitry may contain a programmable load that may be programmed to have a characteristic time. Programmable delay test circuitry may assert an error signal when the delay time is greater than the characteristic time of the test circuitry.

摘要翻译： 提供可编程延迟测试电路，用于在集成电路上测试被测电路。 当被测电路提供的延迟时间大于可编程到可编程延迟测试电路中的特征时间时，延迟测试电路可以使用逻辑电路来输出误差信号。 可编程延迟测试电路可以使用逻辑门来提供具有等于延迟电路的延迟的脉冲宽度的脉冲。 可编程延迟测试电路可以包含可编程为具有特征时间的可编程负载。 当延迟时间大于测试电路的特征时间时，可编程延迟测试电路可以断言错误信号。

公开(公告)号：US07301836B1

公开(公告)日：2007-11-27

申请号：US11257861

申请日：2005-10-25

申请人： Dhananjay Srinivasa Raghavan ,  Paul J. Tracy

发明人： Dhananjay Srinivasa Raghavan ,  Paul J. Tracy

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G01R31/31932 ,  G01R31/3172 ,  G01R31/31924

摘要： An integrated circuit is provided that includes testing circuitry for testing input-output circuits. The integrated circuit contains input-output circuits that each have associated input-output pins and input and output buffers. Each input-output circuit has associated features such as a weak pull-up feature, a voltage clamp diode feature, a bus hold feature, an open-drain feature, a differential input termination resistance feature, and a single-ended/differential mode selection feature. An input-output feature control register receives input-output circuit feature selection instructions. The feature selection instructions contain feature selection bits whose values determine which of the input-output circuit features are enabled in a set of input-output circuits for testing on the integrated circuit. The feature selection instructions can selectively enable one or more input-output circuit features in each input-output circuit. Different feature selection instructions can be loaded into the feature control register to systematically test the input-output circuit features.

摘要翻译： 提供了一个集成电路，其中包括用于测试输入 - 输出电路的测试电路。 集成电路包含各自具有相关输入输出引脚和输入和输出缓冲器的输入输出电路。 每个输入 - 输出电路都具有相关的功能，如弱上拉功能，电压钳位二极管特性，总线保持功能，开漏特性，差分输入端接电阻特性以及单端/差分模式选择 特征。 输入输出特征控制寄存器接收输入输出电路特征选择指令。 特征选择指令包含特征选择位，其值确定在一组用于在集成电路上进行测试的输入输出电路中使能输入输出电路特征的哪一个。 特征选择指令可以选择性地启用每个输入 - 输出电路中的一个或多个输入 - 输出电路特征。 可以将不同的特征选择指令加载到特征控制寄存器中，以系统地测试输入 - 输出电路特性。