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    Method for classifying errors in the layout of a semiconductor circuit
    1.
    发明授权
    Method for classifying errors in the layout of a semiconductor circuit 有权
    对半导体电路布局中的误差进行分类的方法

    公开(公告)号：US07716613B2

    公开(公告)日：2010-05-11

    申请号：US11712635

    申请日：2007-03-01

    申请人： Dirk Meyer ,  Thomas Roessler

    发明人： Dirk Meyer ,  Thomas Roessler

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method for classifying errors in the layout of a semiconductor circuit includes examining the layout of the semiconductor circuit for infringement of predetermined design rules in order to establish errors. For each error, the error is marked in the layout, and information about the error and the layout of the semiconductor circuit in an area surrounding the error is extracted. The extracted information is compared with prestored information within a multiplicity of classes, and the error is assigned to the respective class on the basis of the compared information.

    摘要翻译： 用于对半导体电路的布局中的误差进行分类的方法包括：检查半导体电路的布局，以便违反预定的设计规则以建立错误。 对于每个错误，在布局中标记错误，并提取关于错误周围区域中的半导体电路的错误和布局的信息。 将所提取的信息与多个类中的预存信息进行比较，并且基于所比较的信息将错误分配给相应的类。

    Method for classifying errors in the layout of a semiconductor circuit
    2.
    发明申请
    Method for classifying errors in the layout of a semiconductor circuit 有权
    对半导体电路布局中的误差进行分类的方法

    公开(公告)号：US20070157142A1

    公开(公告)日：2007-07-05

    申请号：US11712635

    申请日：2007-03-01

    申请人： Dirk Meyer ,  Thomas Roessler

    发明人： Dirk Meyer ,  Thomas Roessler

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method for classifying errors in the layout of a semiconductor circuit includes examining the layout of the semiconductor circuit for infringement of predetermined design rules in order to establish errors. For each error, the error is marked in the layout, and information about the error and the layout of the semiconductor circuit in an area surrounding the error is extracted. The extracted information is compared with prestored information within a multiplicity of classes, and the error is assigned to the respective class on the basis of the compared information.

    摘要翻译： 用于对半导体电路的布局中的误差进行分类的方法包括：检查半导体电路的布局，以便违反预定的设计规则以建立错误。 对于每个错误，在布局中标记错误，并提取关于错误周围区域中的半导体电路的错误和布局的信息。 将所提取的信息与多个类中的预存信息进行比较，并且基于所比较的信息将错误分配给相应的类。

    Method for classifying errors in the layout of a semiconductor circuit
    3.
    发明授权
    Method for classifying errors in the layout of a semiconductor circuit 有权

    公开(公告)号：US07207016B2

    公开(公告)日：2007-04-17

    申请号：US10447386

    申请日：2003-05-29

    申请人： Dirk Meyer ,  Thomas Roessler

    发明人： Dirk Meyer ,  Thomas Roessler

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method for classifying errors in the layout of a semiconductor circuit includes examining the layout of the semiconductor circuit for infringement of predetermined design rules in order to establish errors. For each error, the error is marked in the layout, and information about the error and the layout of the semiconductor circuit in an area surrounding the error is extracted. The extracted information is compared with prestored information within a multiplicity of classes, and the error is assigned to the respective class on the basis of the compared information.

    Evaporative disposable garment
    4.
    发明申请
    Evaporative disposable garment 审中-公开
    蒸发一次性服装

    公开(公告)号：US20060142719A1

    公开(公告)日：2006-06-29

    申请号：US11023710

    申请日：2004-12-28

    申请人： Robert Vogt ,  Michael Garvey ,  Paul Van Gompel ,  Thomas Roessler ,  Rebecca Hayes

    发明人： Robert Vogt ,  Michael Garvey ,  Paul Van Gompel ,  Thomas Roessler ,  Rebecca Hayes

    IPC分类号： A61F13/15

    CPC分类号： A61F13/514 ,  A61F2013/1556 ,  A61F2013/51419

    摘要： A disposable garment having a liquid permeable liner, a liquid impermeable/vapor permeable outer cover in opposed relationship with the liner and an absorbent body disposed between the liner and the outer cover. The outer cover has a water vapor transmission rate (WVTR) as determined by a Water Vapor Transmission Rate Test of at least about 6,000 g/m2/24 hours. The disposable garment has an evaporation rate as determined by an Evaporation Rate Test of at least 0.15 g/hr/in2. A disposable garment is also disclosed having an absorbent body with an evaporation rate as determined by the Evaporation Rate Test of at least 0.30 g/hr/in2, a saturation capacity ratio as determined by a Saturation Capacity Test of at least about 17 grams/gram, and a saturation capacity as determined by the Saturation Capacity Test of at least about 50 grams.

    摘要翻译： 一种具有液体可渗透衬垫的一次性衣服，与衬里相对关系的液体不可渗透/透气的外盖和设置在衬垫和外罩之间的吸收体。 外罩具有由水蒸汽透过率测试确定的至少约6,000g / m 2/24小时的水蒸汽透过率（WVTR）。 一次性衣服具有通过蒸发速率测试确定的蒸发速率至少0.15g / hr / in 2。 还公开了一种一次性衣服，其具有通过蒸发速率测试确定的蒸发速率为至少0.30g / hr / in 2的吸收体，饱和容量比由饱和容量试验 至少约17克/克，饱和容量试验测定的饱和容量为至少约50克。

    METHOD FOR ANALYZING THE DESIGN OF AN INTEGRATED CIRCUIT
    9.
    发明申请
    METHOD FOR ANALYZING THE DESIGN OF AN INTEGRATED CIRCUIT 审中-公开
    分析集成电路设计的方法

    公开(公告)号：US20080147373A1

    公开(公告)日：2008-06-19

    申请号：US11611009

    申请日：2006-12-14

    申请人： Thomas Roessler ,  Markus Hofsaess

    发明人： Thomas Roessler ,  Markus Hofsaess

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/5081

    摘要： According to one aspect, a method for analyzing the design of an integrated circuit comprises performing a simulation of the integrated circuit design to obtain simulation results and automatically associating the obtained simulation results to layout elements of the integrated circuit.

    摘要翻译： 根据一方面，用于分析集成电路的设计的方法包括执行集成电路设计的仿真以获得仿真结果，并将获得的仿真结果自动地与集成电路的布局元素相关联。

    Activatable Fastening System and Web Having Elevated Regions and Functional Material Members
    10.
    发明申请
    Activatable Fastening System and Web Having Elevated Regions and Functional Material Members 有权
    可活动紧固系统和具有高架区域和功能材料成员的网

    公开(公告)号：US20080081147A1

    公开(公告)日：2008-04-03

    申请号：US11942801

    申请日：2007-11-20

    申请人： Jeffrey Lindsay ,  Fung Jou-Chen ,  Thomas Roessler ,  Daniel Ellingson ,  Walter Reade

    发明人： Jeffrey Lindsay ,  Fung Jou-Chen ,  Thomas Roessler ,  Daniel Ellingson ,  Walter Reade

    IPC分类号： B32B3/06

    CPC分类号： A44B18/0015 ,  A44B18/0096 ,  A61F13/625 ,  B24D11/001 ,  C08L2201/12 ,  Y10T24/27 ,  Y10T24/2775 ,  Y10T428/24017 ,  Y10T428/24694

    摘要： A web for use in applying a functional material is provided. The web includes a layer that has a plurality of elevated regions. The layer defines a plurality of cavities such that the cavities are located between adjacent elevated regions. A plurality of depressed regions are located on the layer intermediate the elevated regions. The layer has a longitudinal direction and a longitudinal mid-plane defined therethrough. A plurality of functional material members are located in the cavities of the layer. The functional material members are adapted for adhesion of particles or surfaces thereon. The layer is extendable in the longitudinal direction so that the elevated regions are moved in a direction towards the longitudinal mid-plane.

    摘要翻译： 提供了用于应用功能材料的网。 网包括具有多个升高区域的层。 该层限定多个空腔使得空腔位于相邻的升高区域之间。 多个凹陷区域位于升高区域之上的层上。 该层具有纵向方向和纵向中间平面。 多个功能材料构件位于该层的空腔中。 功能材料构件适于在其上附着颗粒或表面。 该层可以在纵向方向上延伸，使得升高的区域在朝向纵向中间平面的方向上移动。