公开(公告)号：US06956578B2

公开(公告)日：2005-10-18

申请号：US10857173

申请日：2004-05-28

申请人： Dong-Ying Kuo ,  Derek C. Chang

发明人： Dong-Ying Kuo ,  Derek C. Chang

IPC分类号： G09G5/393 ,  G09G5/39

CPC分类号： G09G5/393

摘要： A z-unit for a three-dimensional graphics system is provided having a read buffer and a write buffer. The read buffer stores read requests and the write buffer stores write requests. The read and write requests correspond to atomic operations for z-buffer manipulations. Upon the receipt of a read request, the address of the read request is compared to each of the addresses of the write requests. If a match occurs then the read buffer is flushed until a first read request with the matched address occurs. The write buffer is then flushed and all the write requests within the write buffer is serviced. The read buffer is again flushed until all the read requests within the read buffer is serviced.

公开(公告)号：US6154195A

公开(公告)日：2000-11-28

申请号：US79973

申请日：1998-05-14

申请人： Eric S. Young ,  Randy X. Zhao ,  Anoop Khurana ,  Roger Niu ,  Dong-Ying Kuo ,  Sreenivas R. Kottapalli

发明人： Eric S. Young ,  Randy X. Zhao ,  Anoop Khurana ,  Roger Niu ,  Dong-Ying Kuo ,  Sreenivas R. Kottapalli

IPC分类号： G09G3/20 ,  G09G5/02 ,  G09G5/37 ,  H04N1/405 ,  G09G5/04 ,  G09G5/10 ,  H04N1/40

CPC分类号： H04N1/4051 ,  G09G5/02 ,  G09G3/2051

摘要： A dither unit preferably comprises an offset generator, an adjusted coordinate generator and a dither matrix. The offset generator is coupled to receive information about the relative position of the sub-sample being dithered, and in response generates offset values. The output of the offset generator along with the pixel coordinates are provided to the adjusted coordinate generator which generates adjusted coordinate values used by the dither matrix. The adjusted coordinate values along with a color value are received by the dither matrix, which in response, generates a dithered value for the sub-sample that can be stored back in the over sampling buffer for additional computation.

摘要翻译： 抖动单元优选地包括偏移发生器，调整后的坐标发生器和抖动矩阵。 偏移发生器被耦合以接收关于被抖动的子样本的相对位置的信息，并且作为响应产生偏移值。 偏移发生器的输出以及像素坐标被提供给调整后的坐标发生器，其产生由抖动矩阵使用的调整的坐标值。 调整后的坐标值以及颜色值由抖动矩阵接收，抖动矩阵作为响应，为可以存储在过采样缓冲器中的子样本产生抖动值以用于附加计算。

公开(公告)号：US6144365A

公开(公告)日：2000-11-07

申请号：US60923

申请日：1998-04-15

申请人： Eric S. Young ,  Randy X. Zhao ,  Anoop Khurana ,  Roger Niu ,  Dong-Ying Kuo ,  Sreenivas R. Kottapalli

发明人： Eric S. Young ,  Randy X. Zhao ,  Anoop Khurana ,  Roger Niu ,  Dong-Ying Kuo ,  Sreenivas R. Kottapalli

IPC分类号： G06T15/00 ,  G09G5/10 ,  G09G5/04

CPC分类号： G06T15/005 ,  G09G2340/10

摘要： The present invention provides an alpha blending unit that is able to perform alpha blending on sub-samples of a pixel in an efficient manner. The alpha blending unit preferably comprises a plurality of registers for storing a source color, a blending value, and a plurality of destination sub-sample values, multipliers, adders, an accumulator and a divider. The alpha blending unit advantageously sums the destination sub-sample values and then divides them by the number of sub-samples to generate a combined destination color value. This combined destination color value along with the source color and a blending value are then provided to the multipliers, and adders to generate a new destination color value for the pixel.

摘要翻译： 本发明提供一种能够以有效的方式对像素的子样本进行α混合的α混合单元。 α混合单元优选地包括用于存储源颜色，混合值和多个目标子样本值，乘法器，加法器，累加器和除法器的多个寄存器。 α混合单元有利地将目标子样本值相加，然后将它们除以子样本的数量以生成组合的目标颜色值。 然后将该组合的目的地颜色值以及源颜色和混合值提供给乘法器，并且加法器为像素生成新的目标色彩值。

公开(公告)号：US6011565A

公开(公告)日：2000-01-04

申请号：US057628

申请日：1998-04-09

申请人： Dong-Ying Kuo ,  Zhou Hong ,  Randy Zhao ,  Roger Niu ,  Poornachandra Rao ,  Lin Chen ,  Jeremy Alves

发明人： Dong-Ying Kuo ,  Zhou Hong ,  Randy Zhao ,  Roger Niu ,  Poornachandra Rao ,  Lin Chen ,  Jeremy Alves

IPC分类号： G06T15/00 ,  G06F12/08 ,  G09G5/00

CPC分类号： G06F12/0875 ,  G06F12/0864

摘要： A caching system for increasing the operation concurrency between a cache module and a memory module by comparing received memory block identifiers, which correspond to texels needed for pixel composition, with memory block identifiers corresponding to texels locally stored within the cache module. If the received memory block identifiers match the memory block identifiers corresponding to locally cached texels, the system transmits these texels to a texture filter unit for pixel composition. If the received memory block identifiers do not match memory block identifiers corresponding to the locally cached texels, the system retrieves these texels from the memory module as fast as possible and then updates the cache module with the new texels. A plurality of first in, first out buffers are used to assist a controller module with synchronizing the transmission of the texels from the cache module and the overwriting of the texels received from the memory module into the cache module. Once locally cached, these texels also are transmitted to the texture filter unit for pixel composition.

摘要翻译： 一种缓存系统，用于通过将对应于像素合成所需的纹理元素的接收到的存储器块标识符与对应于本地存储在高速缓存模块中的纹素的存储器块标识符相比较来增加高速缓存模块和存储器模块之间的操作并发性。 如果接收到的存储块标识符与对应于本地缓存的纹素的存储器块标识符相匹配，则系统将这些纹素传送到用于像素组合的纹理滤波器单元。 如果接收到的存储器块标识符与对应于本地缓存的纹素的存储器块标识符不匹配，则系统尽可能快地从存储器模块中检索这些纹素，然后用新的纹素更新缓存模块。 多个先进先出缓冲器用于辅助控制器模块，使来自高速缓存模块的纹素的传输同步，以及将从存储器模块接收的纹素的覆盖写入缓存模块。 一旦本地缓存，这些纹素也被传送到纹理滤波器单元以进行像素组合。

公开(公告)号：US20050007374A1

公开(公告)日：2005-01-13

申请号：US10857173

申请日：2004-05-28

申请人： Dong-Ying Kuo ,  Derek Chang

发明人： Dong-Ying Kuo ,  Derek Chang

IPC分类号： G09G5/393 ,  G09G5/39

CPC分类号： G09G5/393

摘要： A z-unit for a three-dimensional graphics system is provided having a read buffer and a write buffer. The read buffer stores read requests and the write buffer stores write requests. The read and write requests correspond to atomic operations for z-buffer manipulations. Upon the receipt of a read request, the address of the read request is compared to each of the addresses of the write requests. If a match occurs then the read buffer is flushed until a first read request with the matched address occurs. The write buffer is then flushed and all the write requests within the write buffer is serviced. The read buffer is again flushed until all the read requests within the read buffer is serviced.

摘要翻译： 提供了具有读缓冲器和写缓冲器的三维图形系统的z单元。 读取缓冲器存储读取请求，写入缓冲器存储写入请求。 读写请求对应于z缓冲操作的原子操作。 在接收到读请求时，将读请求的地址与写请求的每个地址进行比较。 如果发生匹配，则读取缓冲区被刷新，直到出现匹配地址的第一个读取请求。 然后刷新写入缓冲区，并且对写入缓冲区内的所有写入请求进行处理。 读取缓冲区再次被刷新，直到读取缓冲区中的所有读取请求被服务为止。

公开(公告)号：US06476808B1

公开(公告)日：2002-11-05

申请号：US09419699

申请日：1999-10-14

申请人： Dong-Ying Kuo ,  Mike Hong ,  Fred Liao

发明人： Dong-Ying Kuo ,  Mike Hong ,  Fred Liao

IPC分类号： G06T1500

CPC分类号： G06T15/005

摘要： A token-based buffer system for a geometry pipeline in three-dimensional graphics comprises: a buffer control initialization (BCI) unit, a new token or index module, a geometry control pipeline, a vertex buffer, and a processing engine. The token-based buffer system provides a shared resource environment in which tokens are assigned for blocks of data. Each block of data includes that data necessary for each unit or stage in the geometry pipeline to perform its computation. The use of tokens is advantageous because it optimizes the storage efficiency for storing the blocks of data and ensures the correctness of the data as it is passed between stages.

摘要翻译： 用于三维图形中的几何流水线的基于令牌的缓冲器系统包括：缓冲器控制初始化（BCI）单元，新的令牌或索引模块，几何控制流水线，顶点缓冲器和处理引擎。 基于令牌的缓冲系统提供共享资源环境，其中令牌被分配用于数据块。 每个数据块包括几何流水线中每个单元或阶段执行其计算所需的数据。 使用令牌是有利的，因为它优化了用于存储数据块的存储效率，并确保数据在阶段之间通过时的正确性。

公开(公告)号：US06268874B1

公开(公告)日：2001-07-31

申请号：US09128923

申请日：1998-08-04

申请人： Roger Niu ,  Dong-Ying Kuo ,  Randy X. Zhao ,  Chih-Hong Fu

发明人： Roger Niu ,  Dong-Ying Kuo ,  Randy X. Zhao ,  Chih-Hong Fu

IPC分类号： G06T120

CPC分类号： G06T17/00

摘要： A command parser 308 is coupled to an incoming data stream to insert an end of state token at the end of a group of state data 480 and an end of primitive token at the end of a group of primitive data 484 to create a parsed data stream. The parsed state data stream is transmitted to a state controller 420 which loads state data 480 into shadow stages 412. The state controller 420 validates a shadow stage 412 upon receiving an end of state group token. The parsed primitive data 484 are also transmitted to primitive controllers 424. The primitive controllers 424 prevent primitive data from being transmitted into a processing element 464 responsive to receiving an end of primitive_B token. Upon receiving an end of primitive_E token, the primitive controller 424 ascertains whether the first shadow stage 412 has been validated. If it has, the primitive controller 424 loads the state data 480 into the working stage 406, and allows the primitive data 484 to be transmitted to the processing element 464, where it is processed in accordance with the state data 480 in the working stage 406. In an alternate embodiment, a dirty bit 415 is used to indicate that the state data 480 received by the state controller 420 is identical to previously received state data 480. The primitive controller 424 ascertains whether the dirty bit 415 of the first shadow stage 412 associated with its processing element 464 is marked. If the dirty bit 415 is unmarked, the primitive controller 424 allows the primitive data 484 to be processed by the processing element 464 without delay in accordance with the existing state information in the working registers.

摘要翻译： 命令解析器308耦合到输入数据流，以在一组状态数据480的结尾处插入状态结束标记，并在原始数据组484的末尾插入原始令牌的结尾，以创建解析的数据流 。 解析状态数据流被发送到状态控制器420，状态控制器420将状态数据480加载到阴影阶段412中。状态控制器420在接收状态组令牌结束时验证影子级412。 经解析的原始数据484也被发送到原语控制器424.原语控制器424防止原始数据被发送到响应于接收到原始_B令牌结束的处理元件464。 在接收到primitive_E令牌的结束之后，原语控制器424确定第一影子舞台412是否已被验证。 如果有的话，原语控制器424将状态数据480加载到工作阶段406中，并允许将原始数据484发送到处理单元464，在处理单元464中，根据工作阶段406中的状态数据480进行处理 在替代实施例中，脏位415用于指示由状态控制器420接收的状态数据480与先前接收的状态数据480相同。原语控制器424确定第一影子级412的脏位415 与其处理元件464相关联地被标记。 如果脏位415未标记，则原语控制器424允许根据工作寄存器中的现有状态信息，处理单元464无延迟地处理原语数据484。

公开(公告)号：US5852451A

公开(公告)日：1998-12-22

申请号：US780787

申请日：1997-01-09

申请人： Michael B. Cox ,  Dinyar B. Lahewala ,  Dong-Ying Kuo

发明人： Michael B. Cox ,  Dinyar B. Lahewala ,  Dong-Ying Kuo

IPC分类号： G06F12/02 ,  G06T1/20 ,  G06T1/60 ,  G06T15/10 ,  G09G5/00 ,  G09G5/36

CPC分类号： G06T15/10

摘要： A system and method for reordering memory references for pixels to improved bandwidth and performance in texture mapping systems and other graphics systems by improving memory locality in conventional page-mode memory systems. Pixel memory references are received from a client graphics engine and placed in a pixel priority heap. The pixel priority heap reorders the pixel memory references so that references requiring a currently open page are, in general, processed before references that require page breaks. Reordered pixel memory references are transmitted to a memory controller for accessing memory.

摘要翻译： 一种用于重新排列像素的存储器引用的系统和方法，以通过改进常规页面模式存储器系统中的存储器位置来改善纹理映射系统和其他图形系统中的带宽和性能。 从客户端图形引擎接收像素存储器引用并放置在像素优先级堆中。 像素优先级堆重新排列像素存储器引用，使得通常在需要分页符的引用之前处理需要当前打开的页面的引用。 重新排列的像素存储器引用被发送到存储器控制器以访问存储器。

公开(公告)号：US5561615A

公开(公告)日：1996-10-01

申请号：US348437

申请日：1994-12-02

申请人： Dong-Ying Kuo ,  Louise A. Koss

发明人： Dong-Ying Kuo ,  Louise A. Koss

IPC分类号： H03M7/24 ,  G06F7/00 ,  G06F7/38 ,  G06F15/00

CPC分类号： H03M7/24

摘要： A floating point binary number that is to be converted to a fixed point representation, or a fixed point number to be reduced in precision, is originally located in a source register. A conversion mechanism connects the source register to a destination register. After the conversion the least significant bit of the fixed point representation may deliberately retain an indication of the existence of less significant non-zero bits that were truncated. When such retention is desired it is accomplished by forcing that least significant bit to be a one if the fractional portion of the converted number is zero and there were such truncated non-zero bits of lesser significance. To do this the direction and amount of mantissa shift needed during conversion are inspected to reveal which bit positions in the original floating point number are going to be truncated. An array of two-input AND gates has one AND gate per possible truncated bit. A mask is generated by a lookup table according to the number of bits to be truncated. The mask supplies a logic 1 to one input of each such corresponding gate; the other input of each gate is driven by the bit to be truncated. If any such bit to be truncated is a one, then the output of the corresponding gate will be true. The outputs of all these AND gates or OR'ed together and the result stored in a latch; a SET latch then indicates the impending truncation of at least one 1. After the conversion the fractional portion of the destination register is checked to see if it is all zeros. If it is, and if the latch is also SET, then the least significant bit of the fractional portion of the destination register is forced to be understood as a 1 when the register is read.

摘要翻译： 要转换为固定点表示的浮点二进制数或精度要降低的固定点数最初位于源寄存器中。 转换机制将源寄存器连接到目标寄存器。 在转换之后，固定点表示的最低有效位可以有意地保留被截断的不太重要的非零比特的存在的指示。 当需要这样的保持时，如果转换的数字的小数部分为零并且存在具有较小重要性的截断的非零位，则迫使该最低有效位为一。 为此，检查转换期间所需的尾数偏移的方向和量，以显示原始浮点数将被截断的位位置。 两个输入“与”门的阵列每个可能的截断位具有一个与门。 根据要截断的比特数，通过查找表生成掩码。 掩模提供逻辑1到每个这样的对应门的一个输入; 每个门的另一个输入由被截断的位驱动。 如果要截断的任何这样的位是一个，则相应门的输出将为真。 所有这些与门的输出或“或”在一起，结果存储在锁存器中; SET锁定器然后指示即将截断的至少一个1.在转换之后，检查目的地寄存器的小数部分以查看它是否全为零。 如果是，并且如果锁存器也是SET，则当读取寄存器时，目的地寄存器的小数部分的最低有效位被强制地被理解为1。

公开(公告)号：US06756986B1

公开(公告)日：2004-06-29

申请号：US09420047

申请日：1999-10-18

申请人： Dong-Ying Kuo ,  Derek C. Chang

发明人： Dong-Ying Kuo ,  Derek C. Chang

IPC分类号： G09G539

CPC分类号： G09G5/393

摘要： A z-unit for a three-dimensional graphics system is provided having a read buffer and a write buffer. The read buffer stores read requests and the write buffer stores write requests. The read and write requests correspond to atomic operations for z-buffer manipulations. Upon the receipt of a read request, the address of the read request is compared to each of the addresses of the write requests. If a match occurs then the read buffer is flushed until a first read request with the matched address occurs. The write buffer is then flushed and all the write requests within the write buffer is serviced. The read buffer is again flushed until all the read requests within the read buffer is serviced.

摘要翻译： 提供了具有读缓冲器和写缓冲器的三维图形系统的z单元。 读取缓冲器存储读取请求，写入缓冲器存储写入请求。 读写请求对应于z缓冲操作的原子操作。 在接收到读请求时，将读请求的地址与写请求的每个地址进行比较。 如果发生匹配，则读取缓冲区被刷新，直到出现匹配地址的第一个读取请求。 然后刷新写入缓冲区，并且对写入缓冲区内的所有写入请求进行处理。 读取缓冲区再次被刷新，直到读取缓冲区中的所有读取请求被服务为止。