公开(公告)号：US08838878B2

公开(公告)日：2014-09-16

申请号：US12791767

申请日：2010-06-01

申请人： Siamak Arya ,  Dongsheng Xing

发明人： Siamak Arya ,  Dongsheng Xing

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7203

摘要： A method of operating a controller for controlling the programming of a NAND memory chip is shown. The NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum erasable unit. The method comprising storing in a temporary storage a first plurality of groups of data, wherein each of the groups of data is to be stored in a block of the NAND memory chip. Each group of data is indexed to the block with which it is to be stored. Finally, the groups of data associated with the same block are programmed into the same block in the same programming operation.

摘要翻译： 示出了操作用于控制NAND存储器芯片的编程的控制器的方法。 NAND存储器芯片具有多个块，每个块具有一定量的存储，其中每个块中的存储量是最小可擦除单元。 该方法包括在临时存储器中存储第一组多组数据，其中数据组中的每一组将被存储在NAND存储器芯片的块中。 每组数据都被索引到要存储的块中。 最后，在相同的编程操作中，与相同块相关联的数据组被编程到相同的块中。

公开(公告)号：US6141251A

公开(公告)日：2000-10-31

申请号：US494185

申请日：2000-01-28

申请人： Dongsheng Xing

发明人： Dongsheng Xing

IPC分类号： G11C16/08 ,  G11C16/04

CPC分类号： G11C16/08

摘要： In a non-volatile memory array where the memory cells in a sector are programmed together and a plurality of sectors form a segment which are erased together, through the use of a free list linking entries in a register with each entry in a register corresponding to a free segment, a free list table is created which readily simplifies searches for segments that are available for erasure. In addition, through the creation of a segment number table and a count index, determination of particular valid sectors in particular segments can be readily identified.

摘要翻译： 在非易失性存储器阵列中，扇区中的存储器单元被编程在一起，并且多个扇区形成被一起擦除的段，通过使用将寄存器中的条目链接到与 一个空闲的段，创建一个免费的列表表，它可以简化搜索可用于擦除的段。 此外，通过创建段号表和计数索引，可以容易地确定特定段中特定有效扇区的确定。

公开(公告)号：US5982665A

公开(公告)日：1999-11-09

申请号：US280255

申请日：1999-03-29

申请人： Dongsheng Xing ,  Simpson (ShinChu) Tao ,  Frank (Fong-Long) Lin

发明人： Dongsheng Xing ,  Simpson (ShinChu) Tao ,  Frank (Fong-Long) Lin

IPC分类号： G11C16/16 ,  G11C16/06

CPC分类号： G11C16/16

摘要： A non-volatile memory device has a plurality of blocks each of which can be erased simultaneously. Each block has a plurality of sectors. A status byte comprising of non-volatile memory cells is associated with each sector. A status circuit receives signals stored in each of the status bytes and generates a status signal indicative of the status of the block.

摘要翻译： 非易失性存储器件具有可以同时擦除的多个块。 每个块具有多个扇区。 包括非易失性存储器单元的状态字节与每个扇区相关联。 状态电路接收存储在每个状态字节中的信号，并产生指示块的状态的状态信号。

公开(公告)号：US08290154B2

公开(公告)日：2012-10-16

申请号：US12761852

申请日：2010-04-16

申请人： Zhenfu Cao ,  Huang Lin ,  Xiaolei Dong ,  Xiaohui Liang ,  Dongsheng Xing

发明人： Zhenfu Cao ,  Huang Lin ,  Xiaolei Dong ,  Xiaohui Liang ,  Dongsheng Xing

IPC分类号： H04L9/00

CPC分类号： H04H60/15 ,  H04H60/23 ,  H04L9/0836 ,  H04L9/0847 ,  H04L2209/601

摘要： Methods and apparatuses for key generation, encryption and decryption in broadcast encryption. A public parameter and a primary key based on a first random number are generated. For each of leaf nodes in a binary tree, a right key set of the leaf node is calculated, the right key set including a right key of the leaf node and right keys of right brother nodes for all the nodes on a path from a root node to the leaf node. A left key set of the leaf node is calculated, the left key set including a left key of the leaf node and left keys of left brother nodes for all the nodes on the path. The sum of the second and third random numbers equals to the first random number. The second random number is different for different subscribers.

摘要翻译： 广播加密中密钥生成，加密和解密的方法和装置。 生成基于第一随机数的公共参数和主键。 对于二叉树中的每个叶节点，计算叶节点的右键集合，右键集合包括来自根的路径上的所有节点的叶节点和右兄弟节点的右键的右键 节点到叶节点。 计算叶节点的左键集，左键集包括叶节点的左键和路径上所有节点的左兄弟节点左键。 第二和第三随机数的和等于第一个随机数。 不同用户的第二个随机数是不同的。

公开(公告)号：US20110296080A1

公开(公告)日：2011-12-01

申请号：US12791767

申请日：2010-06-01

申请人： Siamak Arya ,  Dongsheng Xing

发明人： Siamak Arya ,  Dongsheng Xing

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7203

摘要： A method of operating a controller for controlling the programming of a NAND memory chip is shown. The NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum erasable unit. The method comprising storing in a temporary storage a first plurality of groups of data, wherein each of the groups of data is to be stored in a block of the NAND memory chip. Each group of data is indexed to the block with which it is to be stored. Finally, the groups of data associated with the same block are programmed into the same block in the same programming operation.

摘要翻译： 示出了操作用于控制NAND存储器芯片的编程的控制器的方法。 NAND存储器芯片具有多个块，每个块具有一定量的存储，其中每个块中的存储量是最小可擦除单元。 该方法包括在临时存储器中存储第一组多组数据，其中数据组中的每一组将被存储在NAND存储器芯片的块中。 每组数据都被索引到要存储的块中。 最后，在相同的编程操作中，与相同块相关联的数据组被编程到相同的块中。

公开(公告)号：US06427186B1

公开(公告)日：2002-07-30

申请号：US09281630

申请日：1999-03-30

申请人： Frank (Fong-Long) Lin ,  Dongsheng Xing

发明人： Frank (Fong-Long) Lin ,  Dongsheng Xing

IPC分类号： G06F1210

CPC分类号： G11C16/105 ,  G06F12/0246 ,  G11C16/102

摘要： A memory system, an interface system for accessing a physical sector on an electrically erasable media based upon a logical block number, and a method for mapping a logical block number to a physical sector on an electrically erasable media are disclosed. The erasable media has an erase block size larger than a write block size. The interface system interfaces a host processor to an electrically-erasable memory, such as a flash media. The host processor requests access to the memory based on a logical block number. The interface system uses a first portion of the logical block number to determine from a master index table a physical sector number of a table of physical sector numbers corresponding to the logical block number. The interface system uses a second portion of the logical block number to determine from the table of physical sector numbers the physical sector number on the media corresponding to the logical block number. The host processor is provided access to the physical sector having the physical sector number corresponding to the logical block number. A logical block number may be remapped to a physical sector that has been completely erased by updating the table of physical sector numbers corresponding to the logical block number. A plurality of physical sectors, which are marked as discarded are erased simultaneously.

摘要翻译： 公开了一种存储系统，用于基于逻辑块号访问电可擦除介质上的物理扇区的接口系统，以及用于将逻辑块号映射到电可擦除介质上的物理扇区的方法。 可擦除介质的擦除块大小大于写入块大小。 接口系统将主处理器连接到电可擦除存储器，例如闪存介质。 主处理器基于逻辑块号请求对存储器的访问。 接口系统使用逻辑块号的第一部分从主索引表确定对应于逻辑块号的物理扇区号的表的物理扇区号。 接口系统使用逻辑块号的第二部分从物理扇区号的表中确定媒体上对应于逻辑块号的物理扇区号。 提供主处理器对具有对应于逻辑块号的物理扇区号的物理扇区的访问。 可以通过更新对应于逻辑块号的物理扇区号的表来将逻辑块号重新映射到已被完全擦除的物理扇区。 被标记为被丢弃的多个物理扇区被同时擦除。

公开(公告)号：US06405323B1

公开(公告)日：2002-06-11

申请号：US09281357

申请日：1999-03-30

申请人： Frank Fong-Long Lin ,  Dongsheng Xing

发明人： Frank Fong-Long Lin ,  Dongsheng Xing

IPC分类号： G06F1100

CPC分类号： G11C29/765 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/349 ,  G11C29/88

摘要： A circuit interfaces a host processor to an electrically-erasable memory in a memory space, such as a flash media. The memory space defines a plurality of segments, and each of the segments includes a plurality of sectors. A media interface circuit regulates access by the host processor to the electrically-erasable memory in the memory space. Sector valid indication reading circuitry reads at least one sector valid indication from a segment of the media. Sector valid determination circuitry determines a non-defective sector from the at least one sector valid indication read. Sector level segment defect map indication reading circuitry reads a sector-level segment defect map from the sector determined to be non-defective. Sector defect determination circuitry determines, from the sector-level segment defect map read, sectors within the segment that are valid. Access regulation circuitry regulates access to the memory space at least in part on the determinations by the sector defect determination circuitry.

摘要翻译： 电路将主机处理器与诸如闪存介质之类的存储器空间中的电可擦除存储器接口。 存储器空间定义多个段，并且每个段包括多个扇区。 媒体接口电路调节主处理器对存储器空间中的电可擦除存储器的访问。 扇区有效指示读取电路从介质段读取至少一个扇区有效指示。 扇区有效确定电路从所述至少一个扇区有效指示读取确定无缺陷扇区。 扇区级段缺陷映射指示读取电路从被确定为无缺陷的扇区读取扇区级段缺陷映射。 扇区缺陷确定电路从扇区级段缺陷图读取确定段内的有效段。 访问调节电路至少部分地调节对扇区缺陷确定电路的确定的访问存储器空间。

公开(公告)号：US20130124778A1

公开(公告)日：2013-05-16

申请号：US13293904

申请日：2011-11-10

申请人： Siamak Arya ,  Dongsheng Xing

发明人： Siamak Arya ,  Dongsheng Xing

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7207

摘要： A host device connected to memory devices, with each memory device having NAND memory chips and an associated controller. Each NAND memory chip can store a page of data in a single write operation, and can read a page of data from NAND memory in a single read operation, with the page being the smallest unit of storage and having a plurality of bits. The controller of each memory chip partitions each page of the associated NAND memory chip into first, second and third locations. The first location is for storage of host data. The second location is for storage of controller meta data. The third location is for storage of meta data of the host device associated with the host data. The host data, meta data of the controller, and meta data of the host device are written into or read from a page in a single operation.

摘要翻译： 连接到存储器件的主机设备，每个存储器件具有NAND存储器芯片和相关控制器。 每个NAND存储器芯片可以在单个写入操作中存储一页数据，并且可以在单个读取操作中从NAND存储器读取一页数据，该页面是最小的存储单元并具有多个位。 每个存储器芯片的控制器将相关联的NAND存储器芯片的每一页分成第一，第二和第三位置。 第一个位置用于存储主机数据。 第二个位置用于存储控制器元数据。 第三个位置用于存储与主机数据相关联的主机设备的元数据。 主机数据，控制器的元数据和主机设备的元数据在单个操作中被写入或从页面读取。

公开(公告)号：US20100272260A1

公开(公告)日：2010-10-28

申请号：US12761852

申请日：2010-04-16

申请人： Zhenfu Cao ,  Huang Lin ,  Xiaolei Dong ,  Xiaohui Liang ,  Dongsheng Xing

发明人： Zhenfu Cao ,  Huang Lin ,  Xiaolei Dong ,  Xiaohui Liang ,  Dongsheng Xing

IPC分类号： H04L9/14

CPC分类号： H04H60/15 ,  H04H60/23 ,  H04L9/0836 ,  H04L9/0847 ,  H04L2209/601

摘要： Methods and apparatuses for key generation, encryption and decryption in broadcast encryption. A public parameter and a primary key based on a first random number are generated. For each of leaf nodes in a binary tree, a right key set of the leaf node is calculated, the right key set including a right key of the leaf node and right keys of right brother nodes for all the nodes on a path from a root node to the leaf node. A left key set of the leaf node is calculated, the left key set including a left key of the leaf node and left keys of left brother nodes for all the nodes on the path. The sum of the second and third random numbers equals to the first random number. The second random number is different for different subscribers.

摘要翻译： 广播加密中密钥生成，加密和解密的方法和装置。 生成基于第一随机数的公共参数和主键。 对于二叉树中的每个叶节点，计算叶节点的右键集合，右键集合包括来自根的路径上的所有节点的叶节点和右兄弟节点的右键的右键 节点到叶节点。 计算叶节点的左键集，左键集包括叶节点的左键和路径上所有节点的左兄弟节点左键。 第二和第三随机数的和等于第一个随机数。 不同用户的第二个随机数是不同的。

公开(公告)号：US20100199020A1

公开(公告)日：2010-08-05

申请号：US12365829

申请日：2009-02-04

申请人： Fong-Long Lin ,  Prasanth Kumar ,  Dongsheng Xing

发明人： Fong-Long Lin ,  Prasanth Kumar ,  Dongsheng Xing

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7202

摘要： In the present invention a non-volatile memory subsystem comprises a non-volatile memory device and a memory controller. The memory controller controls the operation of the non-volatile memory device with the memory controller having a processor for executing computer program instructions for partitioning the non-volatile memory device into a plurality of partitions, with each partition having adjustable parameters for wear level and data retention. The memory subsystem also comprises a clock for supplying timing signals to the memory controller.

摘要翻译： 在本发明中，非易失性存储器子系统包括非易失性存储器件和存储器控制器。 存储器控制器控制非易失性存储器设备的操作，存储器控制器具有用于执行用于将非易失性存储器设备划分成多个分区的计算机程序指令的处理器，每个分区具有用于磨损水平和数据的可调参数 保留。 存储器子系统还包括用于向存储器控制器提供定时信号的时钟。