公开(公告)号：US20110310296A1

公开(公告)日：2011-12-22

申请号：US13157950

申请日：2011-06-10

申请人： Chongho Lee ,  Sunghoon Kim ,  Sungwon Kim ,  Dongwon Park

发明人： Chongho Lee ,  Sunghoon Kim ,  Sungwon Kim ,  Dongwon Park

IPC分类号： H03L7/00

CPC分类号： G09G5/008 ,  G09G3/2096 ,  G09G2370/14

摘要： A method for recovering pixel clocks based on an iDP interface includes selecting a prime factor closest to VA or HA from prime factors of X, and selecting a value obtained by subtracting VA from the selected prime factor, as VB, in Mvid = ( HA + HB ) × ( VA + VB ) X , where HA indicates a horizontal active period, HB indicates a horizontal blank interval, VA indicates a vertical active period, and VB indicates a vertical blank interval, fixing the selected VB value, and selecting a total of HB within one frame period and the number of lanes under a condition that Mvid has an integer value, and recovering pixel clocks by multiplying a frequency of link symbol clocks of data received via the lanes by a multiplication of Mvid/48.

摘要翻译： 用于基于iDP接口恢复像素时钟的方法包括从素数因子X中选择最接近VA或HA的素数因子，并且选择通过从所选素数因子中减去VA获得的值作为VB，在Mvid =（HA + HB）×（VA + VB）X，其中HA表示水平有效期，HB表示水平空白间隔，VA表示垂直有效期，VB表示垂直空白间隔，固定所选择的VB值， 在一个帧周期内的HB和在Mvid具有整数值的条件下的通道数，并且通过乘以通过车道接收的数据的链路符号时钟的频率乘以Mvid / 48来恢复像素时钟。

公开(公告)号：US08463965B2

公开(公告)日：2013-06-11

申请号：US13157061

申请日：2011-06-09

申请人： Dongwon Park ,  Sunghoon Kim ,  Sungwon Kim ,  Chongho Lee

发明人： Dongwon Park ,  Sunghoon Kim ,  Sungwon Kim ,  Chongho Lee

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F3/147

摘要： An iDP interface test method includes transmitting test clocks to an iDP sink device; determining whether or not a link clock lock operation in the iDP sink device is successful based on a measurement result of an HPD signal when a clock lock operation for the test clocks is performed; transmitting test data and arbitrary video data to the iDP sink device if the link clock lock operation in the iDP sink device is successful; determining whether or not a symbol lock operation in the iDP sink device is successful when the symbol lock operation for the test data and the arbitrary video data is performed; and comparing a count result with a predetermined reference value, and determining link stability of the iDP sink device based on the comparison result.

摘要翻译： iDP接口测试方法包括将测试时钟发送到iDP宿设备; 当执行用于测试时钟的时钟锁定操作时，基于HPD信号的测量结果，确定iDP宿设备中的链路时钟锁定操作是否成功; 如果iDP宿设备中的链路时钟锁定操作成功，则将测试数据和任意视频数据发送到iDP宿设备; 当执行测试数据和任意视频数据的符号锁定操作时，确定iDP宿设备中的符号锁定操作是否成功; 以及将计数结果与预定参考值进行比较，并且基于比较结果确定iDP宿设备的链路稳定性。

公开(公告)号：US08400567B2

公开(公告)日：2013-03-19

申请号：US13157950

申请日：2011-06-10

申请人： Chongho Lee ,  Sunghoon Kim ,  Sungwon Kim ,  Dongwon Park

发明人： Chongho Lee ,  Sunghoon Kim ,  Sungwon Kim ,  Dongwon Park

IPC分类号： H03L7/00

CPC分类号： G09G5/008 ,  G09G3/2096 ,  G09G2370/14

摘要： A method for recovering pixel clocks based on an iDP interface includes selecting a prime factor closest to VA or HA from prime factors of X, and selecting a value obtained by subtracting VA from the selected prime factor, as VB, in Mvid = ( HA + HB ) × ( VA + VB ) X , where HA indicates a horizontal active period, HB indicates a horizontal blank interval, VA indicates a vertical active period, and VB indicates a vertical blank interval, fixing the selected VB value, and selecting a total of HB within one frame period and the number of lanes under a condition that Mvid has an integer value, and recovering pixel clocks by multiplying a frequency of link symbol clocks of data received via the lanes by a multiplication of Mvid/48.

摘要翻译： 用于基于iDP接口恢复像素时钟的方法包括从素数因子X中选择最接近VA或HA的素数因子，并且选择通过从所选素数因子中减去VA获得的值作为VB，在Mvid =（HA + HB）×（VA + VB）X，其中HA表示水平有效期，HB表示水平空白间隔，VA表示垂直有效期，VB表示垂直空白间隔，固定所选择的VB值， 在一个帧周期内的HB和在Mvid具有整数值的条件下的通道数，并且通过乘以通过车道接收的数据的链路符号时钟的频率乘以Mvid / 48来恢复像素时钟。

公开(公告)号：US20110310252A1

公开(公告)日：2011-12-22

申请号：US13157061

申请日：2011-06-09

申请人： Dongwon Park ,  Sunghoon Kim ,  Sungwon Kim ,  Chongho Lee

发明人： Dongwon Park ,  Sunghoon Kim ,  Sungwon Kim ,  Chongho Lee

IPC分类号： H04N17/04

CPC分类号： G06F3/147

摘要： An iDP interface test method includes transmitting test clocks to an iDP sink device; determining whether or not a link clock lock operation in the iDP sink device is successful based on a measurement result of an HPD signal when a clock lock operation for the test clocks is performed; transmitting test data and arbitrary video data to the iDP sink device if the link clock lock operation in the iDP sink device is successful; determining whether or not a symbol lock operation in the iDP sink device is successful when the symbol lock operation for the test data and the arbitrary video data is performed; and comparing a count result with a predetermined reference value, and determining link stability of the iDP sink device based on the comparison result.

摘要翻译： iDP接口测试方法包括将测试时钟发送到iDP宿设备; 当执行用于测试时钟的时钟锁定操作时，基于HPD信号的测量结果，确定iDP宿设备中的链路时钟锁定操作是否成功; 如果iDP宿设备中的链路时钟锁定操作成功，则将测试数据和任意视频数据发送到iDP宿设备; 当执行测试数据和任意视频数据的符号锁定操作时，确定iDP宿设备中的符号锁定操作是否成功; 以及将计数结果与预定参考值进行比较，并且基于比较结果确定iDP宿设备的链路稳定性。

公开(公告)号：US20090002535A1

公开(公告)日：2009-01-01

申请号：US12146966

申请日：2008-06-26

申请人： Dongwon Park ,  Youngjoong Joo

发明人： Dongwon Park ,  Youngjoong Joo

IPC分类号： H01L31/112 ,  H04N5/335

CPC分类号： H04N5/3745 ,  H04N5/3535 ,  H04N5/355 ,  H04N5/363 ,  H04N5/3651

摘要： Devices and methods for improving the dynamic range and signal-to-noise ratio of image sensors. Complementary Metal Oxide Semiconductor (CMOS) image sensors that use at least one CMOS image pixel circuit, and methods that the CMOS image sensor integrated circuit is configured to perform.

摘要翻译： 用于改善图像传感器的动态范围和信噪比的装置和方法。 使用至少一个CMOS图像像素电路的互补金属氧化物半导体（CMOS）图像传感器以及CMOS图像传感器集成电路被配置为执行的方法。

公开(公告)号：US6031982A

公开(公告)日：2000-02-29

申请号：US749861

申请日：1996-11-15

申请人： Ho D. Truong ,  DongWon Park ,  Hyungsuk Yang ,  Seokkyun Jung

发明人： Ho D. Truong ,  DongWon Park ,  Hyungsuk Yang ,  Seokkyun Jung

IPC分类号： H01L27/06 ,  H01L27/118 ,  G06F17/50 ,  H01L27/10

CPC分类号： H01L27/11807

摘要： A group of function cells (e.g., 40), each created from one or more implementations of a fixed basic cell (20), are utilized in designing a layout for at least part of an integrated circuit. Each basic cell implementation contains a plurality of unconnected transistors (Q1-Q10) arranged in a transistor pattern identical to, or a mirror image of, the transistor pattern in each other basic cell implementation. Transistors of a specified polarity type in each basic cell implementation are normally of two or more different current-carrying capabilities. Each function cell has an interconnection network (42-44) for electrically interconnecting transistors in that function cell to perform a specified electronic function. The function cells typically form a cell library from which certain function cells are selected for generating the layout. The present layout technique is particularly applicable to laying out datapath circuitry (90) in an integrated circuit.

摘要翻译： 在设计集成电路的至少一部分的布局时，利用一组由固定基本单元（20）的一个或多个实施方式创建的功能单元（例如40）。 每个基本单元实现包含以彼此相同的基本单元实现中的晶体管图案相同或者与其相反的晶体管图案布置的多个未连接的晶体管（Q1-Q10）。 每个基本单元实现中的特定极性类型的晶体管通常具有两个或多个不同的载流能力。 每个功能单元具有互连网络（42-44），用于将该功能单元中的晶体管电互连以执行指定的电子功能。 功能单元通常形成单元库，从中选择某些功能单元以生成布局。 本布局技术特别适用于在集成电路中布置数据路径电路（90）。