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    Memory apparatus and method
    1.
    发明申请
    Memory apparatus and method 审中-公开
    存储器和方法

    公开(公告)号：US20060268651A1

    公开(公告)日：2006-11-30

    申请号：US11138019

    申请日：2005-05-26

    申请人： Douglas Cutter ,  Christopher Seib

    发明人： Douglas Cutter ,  Christopher Seib

    IPC分类号： G11C8/00

    CPC分类号： G11C8/08

    摘要： A memory structure has a wordline coupled to at least one memory cell and a wordline driver coupled to the wordline. Further, the memory structure has a wordline chopper coupled to the wordline and configured to discharge the wordline, wherein the memory cell is coupled to the wordline between the wordline driver and the wordline chopper.

    摘要翻译： 存储器结构具有耦合到耦合到字线的至少一个存储器单元和字线驱动器的字线。 此外，存储器结构具有耦合到字线并被配置为放出字线的字线斩波器，其中存储器单元耦合到字线驱动器和字线斩波器之间的字线。

    Method and device for testing a sense amp
    2.
    发明申请
    Method and device for testing a sense amp 失效
    检测放大器的方法和装置

    公开(公告)号：US20050152195A1

    公开(公告)日：2005-07-14

    申请号：US11076472

    申请日：2005-03-08

    申请人： Kurt Beigel ,  Douglas Cutter

    发明人： Kurt Beigel ,  Douglas Cutter

    IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56 ,  G11C29/00

    CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

    摘要： As pad of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

    摘要翻译： 作为存储器阵列的焊盘，提供用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

    System and method for testing a processor
    4.
    发明申请
    System and method for testing a processor 有权

    公开(公告)号：US20060290365A1

    公开(公告)日：2006-12-28

    申请号：US11159607

    申请日：2005-06-23

    申请人： Reid Riedlinger ,  Douglas Cutter

    发明人： Reid Riedlinger ,  Douglas Cutter

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2856 ,  G01R31/2858 ,  G06F11/24

    摘要： A processor comprises a chip, a temperature sensing device, a processor core, and a controller. The temperature sensing device, the processor core, and the controller are integrated on the chip. The controller is configured to set, based on the temperature sensing device, the processor core to a plurality of specified operating points to enable testing of the specified operating points. Each of the operating points is defined by a different temperature and frequency combination, and the processor core is configured to run a set of test codes at each of the operating points.