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公开(公告)号：US09556519B2
公开(公告)日：2017-01-31
申请号：US13304676
申请日：2011-11-27
IPC分类号： C23C16/455 , C23C16/44 , B01D50/00 , B01D53/04
CPC分类号： C23C16/45525 , B01D53/0407 , B01D2258/0216 , C23C16/44 , C23C16/4412 , C23C16/45544
摘要： Vapor deposition systems and methods associated with the same are provided. The systems may be designed to include features that can promote high quality deposition; simplify manufacture, modification and use; as well as, reduce the footprint of the system, amongst other advantages.
摘要翻译： 提供蒸气沉积系统和与之相关的方法。 该系统可以被设计成包括能够促进高质量沉积的特征; 简化制造，修改和使用; 以及减少系统的占地面积等优点。
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2.发明授权公开(公告)号：US06269018B1
公开(公告)日：2001-07-31
申请号：US09549171
申请日：2000-04-13
IPC分类号： G11C1122
CPC分类号： H01L27/224 , G11C11/15 , G11C11/16 , G11C13/0069 , G11C2013/0073 , G11C2213/79 , H01L27/228
摘要： A non-volatile memory array includes a plurality of memory cells. Each memory cell includes a magnetic tunnel junction device having a first free ferromagnetic layer, a second free ferromagnetic layer and a highly conductive layer. The first ferromagnetic layer of each magnetic tunnel junction device extends in a direction that is substantially parallel to the second ferromagnetic layer of the magnetic tunnel junction device. The highly conductive layer of each magnetic tunnel junction device is formed between the first ferromagnetic layer and the second ferromagnetic layer of the magnetic tunnel junction device. A write current through each selected memory cell flows into the highly conductive layer and along at least a portion of the highly conductive layer. A self-field associated with the write current changes a first predetermined magnetization of the first and second ferromagnetic layers to a second predetermined magnetization. In a second embodiment, each memory cell includes a magnetic tunnel junction device having a first free ferromagnetic layer, a second pinned ferromagnetic layer, and a tunneling barrier layer formed between the first and second ferromagnetic layers. The first free ferromagnetic layer has a magnetization in a form of a vortex. The second pinned ferromagnetic layer has substantially the same shape as the shape of the first free ferromagnetic layer and a magnetization in a form of a vortex. A write current flows through the memory cell and producing a self-field that changes a magnetic vortex state of the first free ferromagnetic layer from a first predetermined handedness to a second predetermined handedness.
摘要翻译： 非易失性存储器阵列包括多个存储器单元。 每个存储单元包括具有第一自由铁磁层，第二自由铁磁层和高导电层的磁性隧道结器件。 每个磁性隧道结装置的第一铁磁层沿与磁性隧道结装置的第二铁磁层基本平行的方向延伸。 每个磁性隧道结装置的高导电层形成在磁性隧道结装置的第一铁磁层和第二铁磁层之间。 通过每个选定的存储单元的写入电流流入高导电层并且沿着高导电层的至少一部分流动。 与写入电流相关联的自相位将第一和第二铁磁层的第一预定磁化改变为第二预定磁化。 在第二实施例中，每个存储单元包括具有第一自由铁磁层，第二钉扎铁磁层和形成在第一和第二铁磁层之间的隧道势垒层的磁性隧道结器件。 第一自由铁磁层具有涡旋形式的磁化。 第二钉扎铁磁层具有与第一自由铁磁层的形状和涡旋形式的磁化基本相同的形状。 写入电流流过存储器单元并产生将第一自由铁磁层的磁涡流状态从第一预定手性改变为第二预定手性的自场。
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公开(公告)号：US07244997B2
公开(公告)日：2007-07-17
申请号：US10615552
申请日：2003-07-08
CPC分类号： H01L27/226 , H01L27/15 , H01L29/66984 , Y10S977/935
摘要： An electronic system includes a three terminal device having a light emitting portion and a magnetically sensitive portion. The magnetically sensitive portion is for modulating light emission from the light emitting portion. The device is a spin valve transistor having a light-emitting quantum well in its collector. The device can convert a magnetic digital signal to both an electrical digital signal and an optical digital signal, wherein either or both of these signals can be provided as a device output. The magnetically sensitive portion of the device is formed of a pair of magnetically permeable layers. When the layers are aligned electron current can pass through with sufficient energy to reach a quantum well where they recombine, generating light. The device may be used to read a magnetic storage medium, such as a disk drive. Or it can be used to provide a display or a memory array composed of single device magnetic write, optical read memory cells. Amplification can be provided to the transistor by adjusting the collector base voltage to provide secondary electrons by impact ionization to provide greater electron current and a correspondingly larger optical emission signal.
摘要翻译： 电子系统包括具有发光部分和磁敏部分的三端装置。 磁敏部分用于调制来自发光部分的光发射。 该装置是其收集器中具有发光量子阱的自旋阀晶体管。 该装置可以将磁数字信号转换成电数字信号和光数字信号，其中这些信号中的一个或两者可以被提供为设备输出。 该装置的磁敏部分由一对导磁层形成。 当层对准时，电子电流可以通过足够的能量到达量子阱，在那里它们复合，产生光。 该装置可以用于读取磁性存储介质，例如磁盘驱动器。 或者它可以用于提供由单个设备磁性写入，光学读取存储器单元组成的显示器或存储器阵列。 可以通过调节集电极基极电压来提供放大，以通过冲击电离提供二次电子以提供更大的电子电流和相应较大的光发射信号。
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公开(公告)号：US06480365B1
公开(公告)日：2002-11-12
申请号：US09458543
申请日：1999-12-09
IPC分类号： G11B5127
CPC分类号： B82Y25/00 , B82Y10/00 , G11B5/332 , G11B5/3903 , G11B5/3909 , G11B5/3967
摘要： A spin valve transistor sensor is provided having a emitter element, a collector element and a common base element. The negatively biased emitter element injects a spin polarized hot electron current into the base element by tunneling from a ferromagnetic pinned layer to a ferromagnetic free layer through a first tunnel barrier layer. The positively biased collector element, comprising a second tunnel barrier layer and a nonmagnetic metal layer, collects the fraction of the hot electron current that passes through the base element and over the barrier height of the second tunnel barrier layer. The hot electron current is strongly spin polarized and due to the GMR effect in the magnetic tunnel junction element, the magnitude of the base-collector current is strongly dependent on external magnetic (signal) fields. A process is provided for fabrication of a spin valve transistor sensor suitable for high density magnetic recording applications.
摘要翻译： 提供了具有发射极元件，集电极元件和公共基底元件的自旋阀晶体管传感器。 负偏置的发射极元件通过穿过第一隧道势垒层从铁磁性钉扎层隧穿到铁磁自由层，将自旋极化的热电子流注入基体元件。 包含第二隧道势垒层和非磁性金属层的正偏置集电极元件收集穿过基体元件并在第二隧道势垒层的势垒高度上的热电子流的一部分。 热电子电流是强自旋极化的，并且由于磁性隧道结元件中的GMR效应，基极集电极电流的大小强烈依赖于外部磁（信号）场。 提供了一种制造适用于高密度磁记录应用的自旋阀晶体管传感器的方法。
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公开(公告)号：US07821363B2
公开(公告)日：2010-10-26
申请号：US12032109
申请日：2008-02-15
IPC分类号： H01H51/22
CPC分类号： G11C11/50 , G11C23/00 , H01H1/0094
摘要： An electronic circuit is formed by closely spacing metallic gate and drain interconnects to a flexible portion of a source interconnect. A gate voltage results in electrostatic attraction and lateral mechanical movement of the flexible source interconnect portion and causes an electrical short between source and drain. VanderWaals attraction between contacting source and drain can be used to provide volatile switching (springy thicker source portion) and non-volatile switching (limp thinner source portion). In accordance with the invention, an easily fabricated, high speed, low power, radiation hard, temperature independent, integrated reconfigurable electronic circuit with embedded logic and non-volatile memory can be realized. The switch uses patterned interconnect material for its structure and can be incorporated to a 3D layered structure consisting of three dimensional interconnect in which different layers and portions of the circuits are linked through volatile and non-volatile switches.
摘要翻译： 电子电路通过将金属栅极和漏极互连紧密地间隔到源互连的柔性部分而形成。 栅极电压导致柔性源互连部分的静电吸引和横向机械移动，并且在源极和漏极之间引起电短路。 VanderWaals接触源极和漏极之间的吸引力可用于提供易失性开关（弹性较厚的源极部分）和非易失性开关（跛行较薄的源极部分）。 根据本发明，可以实现具有嵌入式逻辑和非易失性存储器的易于制造，高速度，低功率，辐射硬，不依赖于温度的集成可重构电子电路。 开关使用图案化的互连材料作为其结构，并且可以结合到由三维互连组成的3D分层结构，其中不同的层和部分电路通过易失性和非易失性开关连接。
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公开(公告)号：US20080185271A1
公开(公告)日：2008-08-07
申请号：US12032109
申请日：2008-02-15
IPC分类号： H01H57/00
CPC分类号： G11C11/50 , G11C23/00 , H01H1/0094
摘要： An electronic circuit is formed by closely spacing metallic gate and drain interconnects to a flexible portion of a source interconnect. A gate voltage results in electrostatic attraction and lateral mechanical movement of the flexible source interconnect portion and causes an electrical short between source and drain. VanderWaals attraction between contacting source and drain can be used to provide volatile switching (springy thicker source portion) and non-volatile switching (limp thinner source portion). In accordance with the invention, an easily fabricated, high speed, low power, radiation hard, temperature independent, integrated reconfigurable electronic circuit with embedded logic and non-volatile memory can be realized. The switch uses patterned interconnect material for its structure and can be incorporated to a 3D layered structure consisting of three dimensional interconnect in which different layers and portions of the circuits are linked through volatile and non-volatile switches.
摘要翻译： 电子电路通过将金属栅极和漏极互连紧密地间隔到源互连的柔性部分而形成。 栅极电压导致柔性源互连部分的静电吸引和横向机械移动，并且在源极和漏极之间引起电短路。 VanderWaals接触源极和漏极之间的吸引力可用于提供易失性开关（弹性较厚的源极部分）和非易失性开关（跛行较薄的源极部分）。 根据本发明，可以实现具有嵌入式逻辑和非易失性存储器的易于制造，高速度，低功率，辐射硬，温度独立的集成可重新配置的电子电路。 开关使用图案化的互连材料作为其结构，并且可以结合到由三维互连组成的3D分层结构，其中不同的层和部分电路通过易失性和非易失性开关连接。
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公开(公告)号：US07355258B2
公开(公告)日：2008-04-08
申请号：US11195064
申请日：2005-08-02
IPC分类号： H01L29/84
CPC分类号： G11C11/50 , G11C23/00 , H01H1/0094
摘要： An electronic circuit is formed by closely spacing metallic gate and drain interconnects to a flexible portion of a source interconnect. A gate voltage results in electrostatic attraction and lateral mechanical movement of the flexible source interconnect portion and causes an electrical short between source and drain. VanderWaals attraction between contacting source and drain can be used to provide volatile switching (springy thicker source portion) and non-volatile switching (limp thinner source portion). In accordance with the invention, an easily fabricated, high speed, low power, radiation hard, temperature independent, integrated reconfigurable electronic circuit with embedded logic and non-volatile memory can be realized. The switch uses patterned interconnect material for its structure and can be incorporated to a 3D layered structure consisting of three dimensional interconnect in which different layers and portions of the circuits are linked through volatile and non-volatile switches.
摘要翻译： 电子电路通过将金属栅极和漏极互连紧密地间隔到源互连的柔性部分而形成。 栅极电压导致柔性源互连部分的静电吸引和横向机械移动，并且在源极和漏极之间引起电短路。 VanderWaals接触源极和漏极之间的吸引力可用于提供易失性开关（弹性较厚的源极部分）和非易失性开关（跛行较薄的源极部分）。 根据本发明，可以实现具有嵌入式逻辑和非易失性存储器的易于制造，高速度，低功率，辐射硬，不依赖于温度的集成可重构电子电路。 开关使用图案化的互连材料作为其结构，并且可以结合到由三维互连组成的3D分层结构，其中不同的层和部分电路通过易失性和非易失性开关连接。
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8.发明授权Magnetic random access memory using a non-linear memory element select mechanism 有权磁性随机存取存储器采用非线性存储元件选择机制公开(公告)号：US06515897B1
公开(公告)日：2003-02-04
申请号：US09549211
申请日：2000-04-13
IPC分类号： G11C1115
CPC分类号： G11C11/15
摘要： A non-volatile memory array having a substrate, a first plurality of electrically conductive traces formed on the substrate, a second plurality of electrically conductive traces formed on the substrate and overlapping first plurality of traces at a plurality of intersection regions, and a plurality of memory cells. Each memory cell is located at an intersection region between one of the first plurality of traces and one of the second plurality of traces. At least one memory cell includes a non-linear magnetic tunnel junction storage element. The non-linear magnetic tunnel junction storage element has at least a first ferromagnetic layer, a barrier layer and a second ferromagnetic layer. The non-linear magnetic tunnel junction storage element has a non-linearity that is defined by a current having a first magnitude flowing through the non-linear magnetic tunnel junction storage element for a bias across the non-linear magnetic tunnel junction storage element of about 0.5 VA that is ten times or more smaller than a current having a second magnitude flowing through the non-linear magnetic tunnel junction storage element for a bias across the non-linear magnetic tunnel junction storage element of about 1 VA, where VA is an operating voltage for a memory cell. The non-linearity is used for minimizing sneak currents through unselected cells, and allowing read or write selection of a particular memory element in a large array.
摘要翻译： 一种非易失性存储器阵列，其具有衬底，形成在衬底上的第一多个导电迹线，形成在衬底上的第二多个导电迹线，并且在多个交叉区域上与第一多个迹线重叠， 记忆细胞 每个存储器单元位于第一多个迹线之一和第二多个迹线中的一个之间的交叉区域。 至少一个存储单元包括非线性磁性隧道结存储元件。 非线性磁性隧道结存储元件具有至少第一铁磁层，阻挡层和第二铁磁层。 非线性磁性隧道结存储元件具有非线性，其由具有流过非线性磁性隧道结存储元件的第一幅度的电流限定，用于横跨非线性磁性隧道结存储元件的偏置约为 0.5VA是比具有第二幅度的电流的十倍或更小，该电流流过非线性磁性隧道结存储元件，用于跨过非线性磁性隧道结存储元件的约1VA的偏压，其中VA是操作的 一个存储单元的电压。 非线性用于通过未选择的单元最小化潜行电流，并允许以大阵列对特定存储器元件进行读取或写入选择。
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9.发明授权Magnetic random access memory using a series tunnel element select mechanism 有权磁性随机存取存储器采用串联隧道元素选择机制公开(公告)号：US06331944B1
公开(公告)日：2001-12-18
申请号：US09549172
申请日：2000-04-13
IPC分类号： G11C1300
CPC分类号： H01L27/224 , G11C11/15
摘要： A non-volatile memory array includes first and second pluralities of electrically conductive traces formed on a substrate. The second plurality of electrically conductive traces overlap first plurality of traces at a plurality of intersection regions. Each of a plurality of memory cells is located at an intersection region between one of the first plurality of traces and one of the second plurality of traces. At least one of the memory cells includes a non-linear selection element in series with a magnetic tunnel junction storage element. The non-linear selection element includes at least a first metallic electrode layer, a barrier layer and a second metallic electrode layer metal. The non-linear selection element has a non-linearity defined by a current having a first magnitude flowing through the non-linear selection element for a first bias voltage across the non-linear selection element that is ten times or more smaller than a current having a second magnitude flowing through the non-linear selection element for a second bias voltage across the non-linear selection element, such that the second bias voltage is about two times greater than the first bias voltage. The magnetic tunnel junction storage element includes at least a first ferromagnetic layer, a thin insulating layer and a second ferromagnetic layer.
摘要翻译： 非易失性存储器阵列包括形成在衬底上的第一和第二多个导电迹线。 第二多个导电迹线在多个交叉区域处与第一多个迹线重叠。 多个存储器单元中的每一个位于第一多个迹线中的一个和第二多个迹线中的一个之间的交叉区域。 至少一个存储单元包括与磁性隧道结存储元件串联的非线性选择元件。 非线性选择元件至少包括第一金属电极层，阻挡层和第二金属电极层金属。 非线性选择元件具有由具有流过非线性选择元件的第一幅度的电流定义的非线性，该电流是非线性选择元件的跨越非线性选择元件的第一偏置电压的十倍或更小， 第二幅度流经所述非线性选择元件，以跨越所述非线性选择元件的第二偏置电压流动，使得所述第二偏置电压大约是所述第一偏置电压的两倍。 磁性隧道结存储元件至少包括第一铁磁层，薄绝缘层和第二铁磁层。
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