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公开(公告)号：US09001558B2
公开(公告)日：2015-04-07
申请号：US14000285
申请日：2012-02-03
申请人： Roland Daniel Rosezin , Florian Lentz , Rainer Bruchhaus , Eike Linn , Ilia Valov , Rainer Waser , Stefan Tappertzhofen , Lutz Nielen
发明人： Roland Daniel Rosezin , Florian Lentz , Rainer Bruchhaus , Eike Linn , Ilia Valov , Rainer Waser , Stefan Tappertzhofen , Lutz Nielen
CPC分类号： G11C13/004 , G11C13/0007 , G11C13/0061 , G11C2013/0073 , G11C2213/73 , G11C2213/76
摘要： A method for reading out a memory element comprises a series connection. of at least two memory cells A and B each have a stable state A0 or B0 having higher resistance and a stable state A1 or B1 having lower electrical resistance. An electrical variable of the series circuit is measured and an electrical variable is selected for this measurement, to which the memory cell A in state A0 makes a different contribution than the memory cell B in state B0 and/or to which the memory cell A instate A1 makes a different contribution than the memory cell B in state B1. The two state combinations A1 and B0 or A0 and B1 then result in differing values for the electrical variable that is measured by way of the series circuit. These state combinations can thus be distinguished from each other without having to change the logic state of the memory element during reading.
摘要翻译： 读出存储元件的方法包括串联连接。 至少两个存储单元A和B各自具有具有较高电阻的稳定状态A0或B0以及具有较低电阻的稳定状态A1或B1。 测量串联电路的电变量，并为此测量选择电变量，状态A0中的存储单元A与状态B0中的存储单元B和/或存储单元A设置的存储单元A的贡献不同 A1在状态B1中与存储单元B的贡献不同。 两个状态组合A1和B0或A0和B1然后导致通过串联电路测量的电变量的不同值。 因此，这些状态组合可以彼此区分，而不必在读取期间改变存储元件的逻辑状态。
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公开(公告)号：US08587988B2
公开(公告)日：2013-11-19
申请号：US13261044
申请日：2010-05-08
CPC分类号： G11C13/0002 , G11C13/00 , G11C13/004 , G11C13/0069 , G11C13/02 , G11C2013/0073 , G11C2213/15 , G11C2213/71 , G11C2213/77 , H03K19/177
摘要： Disclosed is a memory element, a stack, and a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V0, this memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V1, it can be transferred into the likewise high-impedance state 1. By applying a read voltage VR, the magnitude of which is smaller than the write voltages V0 and V1, the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching. A method has been disclosed, using an array comprising the memory elements which can be turned into a gate for arbitrary logic operations.
摘要翻译： 公开了存储元件，堆叠和存储器矩阵，其中可以使用存储元件。 还公开了一种用于操作存储器矩阵的方法，以及用于确定包括存储器元件的阵列中的逻辑运算的真实值的方法。 存储元件具有至少第一稳定状态0和第二稳定状态1.通过施加第一写入电压V0，该存储元件可以被转移到高阻抗状态0并且通过施加第二写入电压V1，它可以 被转移到同样的高阻抗状态1.通过施加其电压值大于写入电压V0和V1的读取电压VR，存储元件表现出不同的电阻值。 在存储矩阵中发生的寄生电流路径中，存储元件充当高阻抗电阻，原则上不限于单极开关。 已经公开了一种使用包括可以变成用于任意逻辑运算的门的存储器元件的阵列的方法。
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公开(公告)号：US20140036574A1
公开(公告)日：2014-02-06
申请号：US14000285
申请日：2012-02-03
申请人： Roland Daniel Rosezin , Florian Lentz , Rainer Bruchhaus , Eike Linn , Ilia Valov , Rainer Waser , Stefan Tappertzhofen , Lutz Nielen
发明人： Roland Daniel Rosezin , Florian Lentz , Rainer Bruchhaus , Eike Linn , Ilia Valov , Rainer Waser , Stefan Tappertzhofen , Lutz Nielen
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0007 , G11C13/0061 , G11C2013/0073 , G11C2213/73 , G11C2213/76
摘要： A method for reading out a memory element comprises a series connection. of at least two memory cells A and B each have a stable state A0 or B0 having higher resistance and a stable state A1 or B1 having lower electrical resistance. An electrical variable of the series circuit is measured and an electrical variable is selected for this measurement, to which the memory cell A in state A0 makes a different contribution than the memory cell B in state B0 and/or to which the memory cell A instate A1 makes a different contribution than the memory cell B in state B1. The two state combinations A1 and B0 or A0 and B1 then result in differing values for the electrical variable that is measured by way of the series circuit. These state combinations can thus be distinguished from each other without having to change the logic state of the memory element during reading.
摘要翻译： 读出存储元件的方法包括串联连接。 至少两个存储单元A和B各自具有具有较高电阻的稳定状态A0或B0以及具有较低电阻的稳定状态A1或B1。 测量串联电路的电变量，并且为该测量选择电变量，状态A0中的存储单元A与状态B0中的存储单元B和/或存储单元A设置的存储单元A的贡献不同 A1在状态B1中与存储单元B的贡献不同。 两个状态组合A1和B0或A0和B1然后导致通过串联电路测量的电变量的不同值。 因此，这些状态组合可以彼此区分，而不必在读取期间改变存储元件的逻辑状态。
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公开(公告)号：US20120087173A1
公开(公告)日：2012-04-12
申请号：US13261044
申请日：2010-05-08
CPC分类号： G11C13/0002 , G11C13/00 , G11C13/004 , G11C13/0069 , G11C13/02 , G11C2013/0073 , G11C2213/15 , G11C2213/71 , G11C2213/77 , H03K19/177
摘要： Disclosed is a memory element, a stack, and a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V0, this memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V1, it can be transferred into the likewise high-impedance state 1. By applying a read voltage VR, the magnitude of which is smaller than the write voltages V0 and V1, the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching. A method has been disclosed, using an array comprising the memory elements which can be turned into a gate for arbitrary logic operations.
摘要翻译： 公开了存储元件，堆叠和存储器矩阵，其中可以使用存储元件。 还公开了一种用于操作存储器矩阵的方法，以及用于确定包括存储器元件的阵列中的逻辑运算的真实值的方法。 存储元件具有至少第一稳定状态0和第二稳定状态1.通过施加第一写入电压V0，该存储元件可以被转移到高阻抗状态0并且通过施加第二写入电压V1，它可以 被转移到同样的高阻抗状态1.通过施加其电压值大于写入电压V0和V1的读取电压VR，存储元件表现出不同的电阻值。 在存储矩阵中发生的寄生电流路径中，存储元件充当高阻抗电阻，原则上不限于单极开关。 已经公开了一种使用包括可以变成用于任意逻辑运算的门的存储器元件的阵列的方法。
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