公开(公告)号：US06793766B2

公开(公告)日：2004-09-21

申请号：US09755516

申请日：2001-01-04

申请人： Eric W. Schieve ,  Lawrence Chung-Lai Lei

发明人： Eric W. Schieve ,  Lawrence Chung-Lai Lei

IPC分类号： C23F100

CPC分类号： H01L21/68 ,  C23C16/54 ,  H01L21/67126 ,  H01L21/67742 ,  Y10S414/135

摘要： Apparatus for processing multiple semiconductor wafers, includes a transfer chamber, a first processing chamber mounted in fixed relation to the transfer chamber and having a first wafer-holding platform with a center, a second processing chamber mounted in adjustable relation to the transfer chamber and to the first chamber and having a second wafer-holding platform with a center, and a robot rotatably mounted within the transfer chamber and having first and second wafer-holding arms spaced parallel to each other for inserting a pair of wafers simultaneously into the first and second chambers and for placing the wafers accurately centered over the respective platforms. The spacing of the platform centers is adjusted relative to the spacing of the robot arms such that the wafers are centered and placed with a preselected degree of accuracy onto the respective platforms for efficient processing of the wafers.

摘要翻译： 用于处理多个半导体晶片的设备包括传送室，第一处理室，其以固定关系安装到传送室，并具有带有中心的第一晶片保持平台，第二处理室以可调节的关系安装在传送室上， 第一腔室和具有中心的第二晶片保持平台，以及可旋转地安装在传送室内的机器，并且具有彼此平行间隔开的​​第一和第二晶片保持臂，用于将一对晶片同时插入到第一和第二腔中 并且用于将晶片准确地放置在各个平台上居中。 平台中心的间距相对于机器人臂的间距进行调节，使得晶片居中并以预选的精确度放置在相应的平台上以有效地处理晶片。

公开(公告)号：US06212651B1

公开(公告)日：2001-04-03

申请号：US08590049

申请日：1996-01-03

申请人： Eric W. Schieve ,  Gary W. Abbott

发明人： Eric W. Schieve ,  Gary W. Abbott

IPC分类号： H02H305

CPC分类号： G06F11/2284

摘要： Disclosed are a system and method for providing fault isolation in a computer system including a central processing unit (“CPU”) capable of issuing a signal to a memory to retrieve a requested instruction from the memory when the CPU is booted. The disclosed invention comprises an interception and substitution circuit, coupled to the CPU, capable of intercepting the signal and providing an alternative diagnostics instruction to the CPU in lieu of the requested instruction, the alternative diagnostics instruction providing an indication of proper functioning of the computer system when executed by the CPU. The circuit allows a user to determine whether the CPU and components proximate the CPU are functioning, even when a fault renders conventional, embedded power-on self-test routines non-functional.

摘要翻译： 公开了一种用于在计算机系统中提供故障隔离的系统和方法，所述系统和方法包括能够在CPU被引导时从存储器发出信号以从存储器检索所请求的指令的中央处理单元（“CPU”）。 所公开的发明包括耦合到CPU的拦截和替换电路，其能够拦截信号并且向CPU提供替代诊断指令来代替所请求的指令，替代诊断指令提供计算机系统的正常功能的指示 当由CPU执行时。 该电路允许用户确定CPU和CPU附近的组件是否正常工作，即使故障使传统的嵌入式开机自检程序无效。

公开(公告)号：US5668980A

公开(公告)日：1997-09-16

申请号：US509487

申请日：1995-07-31

申请人： Eric W. Schieve

发明人： Eric W. Schieve

IPC分类号： G06T3/60 ,  G06F13/00

CPC分类号： G06T3/60

摘要： The invention relates to a method for rotating a source pixel matrix to provide a rotated destination matrix. The method operates on a computer system which includes a processor, a memory and a temporary storage portion. The temporary storage portion includes a plurality of rows where each row includes a plurality of storage locations. The method includes the steps of loading a first set of rows of the temporary storage portion with a lower portion of the source pixel matrix, loading a second set of rows of the temporary storage portion with an upper portion of the source pixel matrix, skewing the source pixel matrix loaded in first and second sets of rows to provide a skewed pixel matrix, alternately rotating selected portions of the skewed pixel matrix stored in selected rows of the first and second sets of rows horizontally and vertically to provide a rotated pixel matrix, and unscrambling the rotated pixel matrix to provide the rotated destination matrix.

摘要翻译： 本发明涉及一种用于旋转源像素矩阵以提供旋转的目的地矩阵的方法。 该方法在包括处理器，存储器和临时存储部分的计算机系统上操作。 临时存储部分包括多行，其中每行包括多个存储位置。 该方法包括以下步骤：将临时存储部分的第一组行加载到源像素矩阵的下部，将临时存储部分的第二组行与源像素矩阵的上部相加， 源像素矩阵，其被加载在第一和第二组行中以提供倾斜的像素矩阵，以水平和垂直方式交替地旋转存储在第一和第二组行的选定行中的偏斜像素矩阵的选定部分以提供旋转的像素矩阵，以及 解开旋转的像素矩阵以提供旋转的目的地矩阵。

公开(公告)号：US5423028A

公开(公告)日：1995-06-06

申请号：US32956

申请日：1993-03-17

申请人： Eric W. Schieve ,  Richard W. Finch

发明人： Eric W. Schieve ,  Richard W. Finch

IPC分类号： G06F11/22 ,  G11C29/08 ,  G06F11/00

CPC分类号： G06F11/2289 ,  G11C29/08

摘要： Disclosed is a diagnostic procedure for identifying and sizing computer memory, which, in the preferred embodiment of the invention, comprises SIMMs. The procedure comprises the steps of (1) testing a plurality of memory locations in the unit by writing and reading bit patterns to memory locations in succession to determine whether any of the memory locations contains any responding bits and (2) stipulating the unit to be present when a number of the memory locations having any responding bits reaches a predetermined minimum number. The procedure is uniquely designed to detect memory which is not fully functional.

摘要翻译： 公开了用于识别和调整计算机存储器的诊断程序，其在本发明的优选实施例中包括SIMM。 该过程包括以下步骤：（1）通过将位模式连续地写入和读取存储器位置来测试单元中的多个存储器位置，以确定存储位置中是否包含任何响应位，以及（2）规定该单元为 当具有任何响应位的数量的存储器位置达到预定的最小数目时存在。 该程序是唯一设计用于检测不完全功能的内存。

公开(公告)号：US07871470B2

公开(公告)日：2011-01-18

申请号：US11426555

申请日：2006-06-26

申请人： Eric W. Schieve ,  Keith K. Koai ,  David T. Or ,  Rene T. Correa

发明人： Eric W. Schieve ,  Keith K. Koai ,  David T. Or ,  Rene T. Correa

IPC分类号： H01L21/00

CPC分类号： H01L21/68742 ,  C23C16/4582 ,  H01L21/68785

摘要： An apparatus for positioning a substrate support within a processing chamber is provided. In one embodiment, an apparatus for positioning a substrate support includes a yoke comprising a curved surface with a first slot formed therethrough, a base comprising a first surface adapted to support the substrate support and a curved second surface, wherein the curved second surface mates with the curved surface of the yoke and a first slot is formed through the curved second surface of the base, and a first threaded member disposed through the first slot in the yoke and the first slot in the base.

摘要翻译： 提供了一种用于将衬底支撑件定位在处理室内的装置。 在一个实施例中，一种用于定位衬底支撑件的装置包括轭，该轭包括具有穿过其形成的第一槽的弯曲表面，基部包括适于支撑衬底支撑件的第一表面和弯曲的第二表面，其中弯曲的第二表面与 轭的弯曲表面和第一槽形成为穿过基座的弯曲的第二表面，并且第一螺纹构件设置成穿过轭的第一槽和基座中的第一槽。

公开(公告)号：US6018808A

公开(公告)日：2000-01-25

申请号：US253480

申请日：1994-06-03

申请人： Eric W. Schieve

发明人： Eric W. Schieve

IPC分类号： G06F11/22 ,  G06F11/267 ,  G06F13/24 ,  G06F13/00

CPC分类号： G06F11/2284 ,  G06F11/2231 ,  G06F13/24

摘要： A read/writable memory formed in the same semiconductor chip as a microprocessor is employed in testing a plurality of hardware interrupt service routines initiated by corresponding devices (and components of devices) during a power-on, self-test(POST) of a computer system. The POST is set in the read-only memory(ROM) of the computer system. The read/writable memory, which is ordinarily inoperative during the POST, is used for storing a diagnostic interrupt vector table, which has a list of interrupt numbers and corresponding addresses of the respective interrupt routines. This table is normally subject to change because each device and each of its components have different interrupt service routines, requiring different addresses for the same interrupt number. The random access memory(RAM) has not yet been tested in the POST, and is not regarded as reliable for the hardware interrupt testing and therefore the read/writable memory is used for such testing.

摘要翻译： 在与计算机相同的半导体芯片中形成的读/写可用存储器用于在计算机的上电，自检（POST）期间测试由相应设备（和设备的组件）发起的多个硬件中断服务程序 系统。 POST设置在计算机系统的只读存储器（ROM）中。 在POST期间通常不工作的读/写可用存储器用于存储诊断中断向量表，其具有中断号列表和相应中断程序的对应地址。 该表通常可能会发生变化，因为每个设备及其每个组件都有不同的中断服务程序，对同一个中断号码需要不同的地址。 随机存取存储器（RAM）尚未在POST中测试，并且不被认为对于硬件中断测试是可靠的，因此读/写可用存储器用于这种测试。

公开(公告)号：US5398333A

公开(公告)日：1995-03-14

申请号：US34056

申请日：1993-03-22

申请人： Eric W. Schieve ,  Richard W. Finch

发明人： Eric W. Schieve ,  Richard W. Finch

IPC分类号： G06F9/445 ,  G06F11/00 ,  G06F11/22 ,  G06F9/00

CPC分类号： G06F9/4401 ,  G06F11/22 ,  G06F11/0757

摘要： Disclosed are a system and method for providing user-invocable, non disk-based diagnostics routines for a personal computer. The method comprises the steps of (1) storing a diagnostics routine capable of performing diagnostic tests on portions of the personal computer in ROM, (2) monitoring a status of a reset button coupled to the personal computer and (3) executing the diagnostics routine if the reset button is pressed twice within a preselected period of time. The disclosed system and method allow a user to control the invocation of a diagnostics routine that needs a minimum of functioning computer hardware to execute.

摘要翻译： 公开了一种用于为个人计算机提供用户可调用的基于非磁盘的诊断程序的系统和方法。 该方法包括以下步骤：（1）存储能够对ROM中的个人计算机的部分执行诊断测试的诊断程序，（2）监视与个人计算机相连的复位按钮的状态，以及（3）执行诊断程序 如果复位按钮在预选的时间段内被按下两次。 所公开的系统和方法允许用户控制需要最小功能的计算机硬件执行的诊断程序的调用。

公开(公告)号：USD643535S1

公开(公告)日：2011-08-16

申请号：US29351402

申请日：2009-12-04

申请人： Christopher G. Ross ,  Terry L. Landis ,  Patrick P. Hicks ,  Eric W. Schieve

设计人： Christopher G. Ross ,  Terry L. Landis ,  Patrick P. Hicks ,  Eric W. Schieve

公开(公告)号：US5511180A

公开(公告)日：1996-04-23

申请号：US43508

申请日：1993-04-06

申请人： Eric W. Schieve

发明人： Eric W. Schieve

IPC分类号： G06F11/22 ,  G11C29/08 ,  G11C29/10 ,  G06F11/00

CPC分类号： G06F11/2289 ,  G11C29/08 ,  G11C29/10

摘要： Disclosed are a circuit and method for dynamically determining cache memory size. The method comprises the steps of (1) writing a replacement data pattern into a first addressable location of a cacheable portion of addressable space, thereby placing the replacement data pattern into a corresponding first addressable location in a cache memory and setting a tag in the first addressable location, (2) accessing an assumed number of remaining addressable locations in the portion of the addressable space thereby setting tags in each of the remaining addressable locations and (3) reading the first addressable location in the cache memory to determine whether the replacement data pattern remains in the first addressable location, the cache memory being of an assumed size if the replacement data pattern is not in the first addressable location in the cache memory. The circuit and method are able to size cache memory without reference to cache size data stored in cache controllers or hardware timers.

摘要翻译： 公开了用于动态地确定高速缓存存储器大小的电路和方法。 该方法包括以下步骤：（1）将替换数据模式写入可寻址空间的可高速缓存部分的第一可寻址位置，从而将替换数据模式置于高速缓冲存储器中相应的第一可寻址位置，并将第一 （2）访问可寻址空间部分中的剩余可寻址位置的假定数目，从而在每个剩余可寻址位置设置标签，并且（3）读取高速缓冲存储器中的第一可寻址位置以确定替换数据 模式保留在第一可寻址位置中，如果替换数据模式不在高速缓冲存储器中的第一可寻址位置，则高速缓冲存储器具有假设大小。 该电路和方法能够对高速缓存存储器进行大小调整，而无需参考高速缓存控制器或硬件定时器中存储的高速缓存大小数据。

公开(公告)号：US5423029A

公开(公告)日：1995-06-06

申请号：US60391

申请日：1993-05-11

申请人： Eric W. Schieve

发明人： Eric W. Schieve

IPC分类号： G06F11/267 ,  G01R31/28 ,  G06F11/00

CPC分类号： G06F11/2221

摘要： Disclosed are an apparatus and method for testing a direct memory access ("DMA") controller. The apparatus comprises (1) a virtual control device including a virtual control latch, the virtual control device coupled to a request input of the DMA controller and capable of transmitting a signal to the DMA controller representing a request to transfer data and (2) a virtual input/output ("I/O") device including a virtual I/O latch, an acknowledgement output of the DMA controller coupled to the virtual I/O device, the virtual I/O latch capable of storing the data for use by the DMA controller. In its preferred embodiment, the present invention operates within the confines of IBM-compatible personal computer architecture, allowing DMA controller functionality to be tested directly.

摘要翻译： 公开了用于测试直接存储器访问（“DMA”）控制器的装置和方法。 该装置包括：（1）虚拟控制装置，包括虚拟控制锁存器，该虚拟控制装置耦合到DMA控制器的请求输入端，并且能够向表示传送数据请求的DMA控制器发送信号;（2） 包括虚拟I / O锁存器的虚拟输入/输出（“I / O”）设备，耦合到虚拟I / O设备的DMA控制器的确认输出，能够存储数据供使用的虚拟I / O锁存器 DMA控制器。 在其优选实施例中，本发明在IBM兼容的个人计算机架构的范围内运行，从而允许直接测试DMA控制器功能。