公开(公告)号：US20080184007A1

公开(公告)日：2008-07-31

申请号：US11498627

申请日：2006-08-02

申请人： Lucian Codrescu ,  Erich Plondke ,  Mao Zeng

发明人： Lucian Codrescu ,  Erich Plondke ,  Mao Zeng

IPC分类号： G06F15/76 ,  G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/30036 ,  G06F9/30112

摘要： A method and system to combine multiple register units within a microprocessor, such as, for example, a digital signal processor, are described. A first register unit and a second register unit are retrieved from a register file structure within a processing unit, the first register unit and the second register unit being non-adjacently located within the register file structure. The first register unit and the second register unit are further combined during execution of a single instruction to form a resulting register unit. Finally, the resulting register unit is stored within the register file structure for further processing. Alternatively, a first half word unit from the first register unit and a second half word unit from the second register unit are retrieved. The first half word unit and the second half word unit are further input into corresponding high and low portions of a resulting register unit to form the resulting register unit during execution of a single instruction. Finally, the resulting register unit is stored within the register file structure for further processing.

摘要翻译： 描述了在微处理器内组合多个寄存器单元的方法和系统，例如数字信号处理器。 从处理单元内的寄存器文件结构检索第一寄存器单元和第二寄存器单元，第一寄存器单元和第二寄存器单元非相邻地位于寄存器堆栈结构内。 在执行单个指令期间，第一寄存器单元和第二寄存器单元进一步组合以形成结果寄存器单元。 最后，所得到的寄存器单元被存储在寄存器堆栈结构中用于进一步处理。 或者，检索来自第一寄存器单元的第一半字单元和来自第二寄存器单元的第二半字单元。 第一半字单元和第二半字单元进一步输入到所得寄存器单元的对应高和低部分，以在单个指令的执行期间形成结果寄存器单元。 最后，所得到的寄存器单元被存储在寄存器堆栈结构中用于进一步处理。

公开(公告)号：US07949701B2

公开(公告)日：2011-05-24

申请号：US11498604

申请日：2006-08-02

申请人： Lucian Codrescu ,  Erich Plondke ,  Mao Zeng

发明人： Lucian Codrescu ,  Erich Plondke ,  Mao Zeng

IPC分类号： G06F7/38 ,  G06F7/00 ,  G06F15/00

CPC分类号： G06F9/30043 ,  G06F9/30014 ,  G06F9/30018

摘要： A method and system to perform shifting and rounding operations within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to shift and round data within a source register unit of a register file structure is received within a processing unit. The instruction includes a shifting bit value indicating the bit amount for a right shift operation and is subsequently executed to shift data within the source register unit to the right by an encoded bit value, calculated by subtracting a single bit from the shifting bit value contained within the instruction. A predetermined bit extension is further inserted within the vacated bit positions adjacent to the shifted data. Subsequently, an addition operation is performed on the shifted data and a unitary integer value is added to the shifted data to obtain resulting data. Finally, the resulting data is further shifted to the right by a single bit value and a predetermined bit extension is inserted within the vacated bit position to obtain the final rounded data results to be stored within a destination register unit.

摘要翻译： 描述了在执行单个指令期间在微处理器（例如数字信号处理器）内执行移位和舍入操作的方法和系统。 在处理单元内接收用于在寄存器堆结构的源寄存器单元内移位和舍入数据的指令。 该指令包括指示右移位操作的位量的移位位值，并且随后被执行以将源寄存器单元内的数据向右移位编码位值，该编码位值通过从包含在其中的移位位值中减去单个位而被计算 指示。 进一步将预定比特扩展插入与移位数据相邻的空闲比特位置。 随后，对移位的数据执行相加操作，并将一个整数值加到移位数据上，以获得结果数据。 最后，所得到的数据进一步向右移位一个位值，并且将预定的位扩展插入到空出的位位置中，以获得存储在目的地寄存器单元内的最终舍入数据结果。

公开(公告)号：US20080034189A1

公开(公告)日：2008-02-07

申请号：US11498604

申请日：2006-08-02

申请人： Lucian Codrescu ,  Erich Plondke ,  Mao Zeng

发明人： Lucian Codrescu ,  Erich Plondke ,  Mao Zeng

IPC分类号： G06F9/44

CPC分类号： G06F9/30043 ,  G06F9/30014 ,  G06F9/30018

摘要： A method and system to perform shifting and rounding operations within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to shift and round data within a source register unit of a register file structure is received within a processing unit. The instruction includes a shifting bit value indicating the bit amount for a right shift operation and is subsequently executed to shift data within the source register unit to the right by an encoded bit value, calculated by subtracting a single bit from the shifting bit value contained within the instruction. A predetermined bit extension is further inserted within the vacated bit positions adjacent to the shifted data. Subsequently, an addition operation is performed on the shifted data and a unitary integer value is added to the shifted data to obtain resulting data. Finally, the resulting data is further shifted to the right by a single bit value and a predetermined bit extension is inserted within the vacated bit position to obtain the final rounded data results to be stored within a destination register unit.

摘要翻译： 描述了在执行单个指令期间在微处理器（例如数字信号处理器）内执行移位和舍入操作的方法和系统。 在处理单元内接收用于在寄存器堆结构的源寄存器单元内移位和舍入数据的指令。 该指令包括指示右移位操作的位量的移位位值，并且随后被执行以将源寄存器单元内的数据向右移位编码位值，该编码位值通过从包含在其中的移位位值中减去单个位而被计算 指示。 进一步将预定比特扩展插入与移位数据相邻的空闲比特位置。 随后，对移位的数据执行相加操作，并将一个整数值加到移位数据上，以获得结果数据。 最后，所得到的数据进一步向右移位一个位值，并且将预定的位扩展插入到空出的位位置中，以获得存储在目的地寄存器单元内的最终舍入数据结果。

公开(公告)号：US08417922B2

公开(公告)日：2013-04-09

申请号：US11498627

申请日：2006-08-02

申请人： Lucian Codrescu ,  Erich Plondke ,  Mao Zeng

发明人： Lucian Codrescu ,  Erich Plondke ,  Mao Zeng

IPC分类号： G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/30036 ,  G06F9/30112

摘要： A method and system to combine multiple register units within a microprocessor, such as, for example, a digital signal processor, are described. A first register unit and a second register unit are retrieved from a register file structure within a processing unit, the first register unit and the second register unit being non-adjacently located within the register file structure. The first register unit and the second register unit are further combined during execution of a single instruction to form a resulting register unit. Finally, the resulting register unit is stored within the register file structure for further processing. Alternatively, a first half word unit from the first register unit and a second half word unit from the second register unit are retrieved. The first half word unit and the second half word unit are further input into corresponding high and low portions of a resulting register unit to form the resulting register unit during execution of a single instruction. Finally, the resulting register unit is stored within the register file structure for further processing.

摘要翻译： 描述了在微处理器内组合多个寄存器单元的方法和系统，例如数字信号处理器。 从处理单元内的寄存器文件结构检索第一寄存器单元和第二寄存器单元，第一寄存器单元和第二寄存器单元非相邻地位于寄存器堆栈结构内。 在执行单个指令期间，第一寄存器单元和第二寄存器单元进一步组合以形成结果寄存器单元。 最后，所得到的寄存器单元被存储在寄存器堆栈结构中用于进一步处理。 或者，检索来自第一寄存器单元的第一半字单元和来自第二寄存器单元的第二半字单元。 第一半字单元和第二半字单元进一步输入到所得寄存器单元的对应高和低部分，以在单个指令的执行期间形成结果寄存器单元。 最后，所得到的寄存器单元被存储在寄存器堆栈结构中用于进一步处理。

公开(公告)号：US20070094478A1

公开(公告)日：2007-04-26

申请号：US11255434

申请日：2005-10-20

申请人： Erich Plondke ,  Lucian Codrescu ,  Muhammad Ahmed ,  Mao Zeng ,  Sujat Jamil ,  William Anderson

发明人： Erich Plondke ,  Lucian Codrescu ,  Muhammad Ahmed ,  Mao Zeng ,  Sujat Jamil ,  William Anderson

IPC分类号： G06F12/00

CPC分类号： G06F5/10 ,  G06F9/3552 ,  G06F9/3851 ,  G06F2205/106

摘要： Techniques for processing digital signals for a variety of applications, including in a communications (e.g., CDMA) system. A pointer location within a circular buffer is determined by establishing a length of the circular buffer, a start address that is aligned to a power of 2, and an end address located distant from the start address by the length and less than a power of 2 greater than the length. The method and system determine a current pointer location for an address within the circular buffer, a stride value of bits between the start address and the end address, a new pointer location within the circular buffer that is shifted from the current pointer location by the number of bits of the stride value. An adjusted pointer location is within the circular buffer by an arithmetic operation of the new pointer location with the length.

摘要翻译： 用于处理包括在通信（例如CDMA）系统中的各种应用的数字信号的技术。 循环缓冲器中的指针位置通过建立循环缓冲器的长度，与2的幂对齐的起始地址和远离起始地址长度并小于2的幂的结束地址来确定 大于长度。 该方法和系统确定循环缓冲器中的地址的当前指针位置，起始地址和结束地址之间的位的步幅值，循环缓冲器内的新指针位置，其从当前指针位置移位数字 的步幅值。 通过具有长度的新指针位置的算术运算，调整的指针位置在循环缓冲器内。

公开(公告)号：US08713286B2

公开(公告)日：2014-04-29

申请号：US11115916

申请日：2005-04-26

申请人： Muhammad Ahmed ,  Erich Plondke ,  Lucian Codrescu ,  William C. Anderson

发明人： Muhammad Ahmed ,  Erich Plondke ,  Lucian Codrescu ,  William C. Anderson

IPC分类号： G06F7/57

CPC分类号： G06F9/30149 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3885

摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.

摘要翻译： 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。 处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。

公开(公告)号：US07917907B2

公开(公告)日：2011-03-29

申请号：US11089474

申请日：2005-03-23

申请人： Muhammad Ahmed ,  Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  William C. Anderson

发明人： Muhammad Ahmed ,  Sujat Jamil ,  Erich Plondke ,  Lucian Codrescu ,  William C. Anderson

IPC分类号： G06F9/46 ,  G06F15/76

CPC分类号： G06F9/3851

摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.

摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 所公开的主题的一个方面包括用于在多线程处理器上处理指令的方法。 多线程处理器经由多个处理器管线处理多个线程。 该方法包括确定多线程处理器工作的工作频率F的步骤。 然后，该方法确定用于触发多个活动线程之间的处理切换的可变线程切换超时状态。 可变线程切换超时状态改变，使得多个活动线程中的每一个以所分配的频率部分F的频率运行。活动线程运行的分配部分至少部分地被确定，以便优化 操作多线程处理器。 在发生可变线程切换超时状态时，该方法还将处理从主动线程中的第一个切换到下一个活动线程。

公开(公告)号：US07685411B2

公开(公告)日：2010-03-23

申请号：US11104115

申请日：2005-04-11

申请人： Muhammad Ahmed ,  Lucian Codrescu ,  Erich Plondke ,  William C. Anderson ,  Robert Allan Lester ,  Phillip M. Jones

发明人： Muhammad Ahmed ,  Lucian Codrescu ,  Erich Plondke ,  William C. Anderson ,  Robert Allan Lester ,  Phillip M. Jones

IPC分类号： G06F9/00

CPC分类号： G06F9/325 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/381

摘要： An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.

摘要翻译： 指令存储单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。 如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别正向程序重定向构造的重复发出，并发出已经存储在第二存储器结构中的下一个程序指令。 第二存储器结构还可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从 如果目标指令没有存储在第二存储器结构中的第一存储器结构。

公开(公告)号：US20060230257A1

公开(公告)日：2006-10-12

申请号：US11104163

申请日：2005-04-11

申请人： Muhammad Ahmed ,  Erich Plondke ,  Lucian Codrescu ,  William Anderson

发明人： Muhammad Ahmed ,  Erich Plondke ,  Lucian Codrescu ,  William Anderson

IPC分类号： G06F9/30

CPC分类号： G06F9/3842 ,  G06F9/3851 ,  G06F9/3885

摘要： A processor device is disclosed and includes a memory unit and at least one interleaved multi-threading instruction pipeline. The interleaved multi-threading instruction pipeline utilizes a number of clock cycles that is less than an instruction issue rate for each of a plurality of program threads that are stored within the memory unit. The memory unit includes six instruction caches. Further, the processor device includes six register files and each of the six register files is associated with one of the six instruction caches. Each of the plurality of program threads is associated with one of the six register files. Further, each of the six program threads includes a plurality of instructions and each of the plurality of instructions is stored within one of the six instruction caches of the memory.

摘要翻译： 公开了处理器设备，并且包括存储器单元和至少一个交错多线程指令流水线。 交错多线程指令流水线利用小于存储在存储器单元内的多个程序线程中的每一个的指令发布速率的多个时钟周期。 存储单元包括六个指令高速缓存。 此外，处理器设备包括六个寄存器文件，六个寄存器文件中的每一个与六个指令高速缓存中的一个相关联。 多个程序线程中的每一个与六个寄存器文件中的一个相关联。 此外，六个程序线程中的每一个包括多个指令，并且多个指令中的每一个被存储在存储器的六个指令高速缓存之一中。

公开(公告)号：US07676647B2

公开(公告)日：2010-03-09

申请号：US11506584

申请日：2006-08-18

申请人： Lucian Codrescu ,  Erich Plondke ,  Taylor Simpson

发明人： Lucian Codrescu ,  Erich Plondke ,  Taylor Simpson

IPC分类号： G06F15/00

CPC分类号： G06F9/30101 ,  G06F9/30021 ,  G06F9/30094 ,  G06F9/3885

摘要： A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation can store resulting bits in the combined condition code register and a conditional operation can utilize the combined condition code register bits for evaluating a condition.

摘要翻译： 公开了一种处理器装置，其包括具有用于标量和矢量操作的组合条件码寄存器的寄存器文件。 处理器设备利用组合条件码寄存器进行标量和矢量操作。 此外，比较操作可以将结果位存储在组合条件码寄存器中，并且条件操作可以利用组合条件码寄存器位来评估条件。