公开(公告)号：US20150146834A1

公开(公告)日：2015-05-28

申请号：US14235242

申请日：2011-07-25

申请人： Andrew Marshall ,  Henry Wong ,  Essaid Bensoudane

发明人： Andrew Marshall ,  Henry Wong ,  Essaid Bensoudane

IPC分类号： H04L7/033

CPC分类号： H04L7/0331 ,  H03L7/0807 ,  H04L7/0025 ,  H04L7/0045 ,  H04L7/005 ,  H04L7/033 ,  H04L25/20

摘要： A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.

摘要翻译： 提供了一种用于减少数字信号中的抖动的电路，包括时钟和数据恢复级，用于接收输入数据信号，并响应于此产生恢复的数据信号，恢复的时钟信号和未滤波的内插器代码; 滤波器级，用于接收未滤波的内插器代码并响应于其产生经滤波的时钟信号; 以及存储组件，用于接收恢复的数据信号，恢复的时钟信号和经滤波的时钟信号; 使用恢复的时钟信号对恢复的数据信号进行采样; 存储所得到的采样位; 并通过使用滤波的时钟信号选择存储的比特来产生输出数据信号。

公开(公告)号：US09444615B2

公开(公告)日：2016-09-13

申请号：US14235242

申请日：2011-07-25

申请人： Andrew Marshall ,  Henry Wong ,  Essaid Bensoudane

发明人： Andrew Marshall ,  Henry Wong ,  Essaid Bensoudane

IPC分类号： H04L7/033 ,  H04L7/00 ,  H03L7/08 ,  H04L25/20

CPC分类号： H04L7/0331 ,  H03L7/0807 ,  H04L7/0025 ,  H04L7/0045 ,  H04L7/005 ,  H04L7/033 ,  H04L25/20

摘要： A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.

摘要翻译： 提供了一种用于减少数字信号中的抖动的电路，包括时钟和数据恢复级，用于接收输入数据信号，并响应于此生成恢复的数据信号，恢复的时钟信号和未滤波的内插器代码; 滤波器级，用于接收未滤波的内插器代码并响应于其产生经滤波的时钟信号; 以及存储组件，用于接收恢复的数据信号，恢复的时钟信号和经滤波的时钟信号; 使用恢复的时钟信号对恢复的数据信号进行采样; 存储所得到的采样位; 并通过选择使用滤波的时钟信号所存储的位产生输出数据信号。