公开(公告)号：US09081708B2

公开(公告)日：2015-07-14

申请号：US13679481

申请日：2012-11-16

申请人： Fuchen Mu ,  Yanzhou Wang

发明人： Fuchen Mu ,  Yanzhou Wang

IPC分类号： G11C29/50 ,  G06F11/10 ,  G11C29/04

CPC分类号： G06F11/1048 ,  G06F11/1008 ,  G06F11/1068 ,  G11C29/50004 ,  G11C2029/0411

摘要： In accordance with at least one embodiment, a method and apparatus for improving the ability to correct errors in memory devices is described. At least one embodiment provides a way to salvage the part even it has double-bit or multi-bit error from the same ECC section, thus improving product reliability and extending the product lifetime. During a normal read, if a double-bit or multiple-bit error happens, which ECC can detect but cannot fix, the error is corrected by adjusting the read voltage level and reading again to determine the proper read level (and, therefore, the correct value being read). This dynamic read scheme can apply to extrinsic bits from either erase state or program state. It can be also used in a single bit scenario to minimize ECC occurrence and save ECC capacity.

摘要翻译： 根据至少一个实施例，描述了一种用于提高校正存储器件中的错误的能力的方法和装置。 至少一个实施例提供了一种挽救部件的方法，即使它具有来自相同ECC部分的双位或多位错误，从而提高产品可靠性并延长产品寿命。 在正常读取期间，如果发生双位或多位错误，哪个ECC可以检测到但无法修复，则通过调整读取电压电平并再次读取来确定正确的读取电平（因此， 读正确值）。 该动态读取方案可以应用于擦除状态或程序状态的外部位。 它也可以用于单个位方案以最小化ECC发生并节省ECC容量。

公开(公告)号：US08995202B2

公开(公告)日：2015-03-31

申请号：US13476711

申请日：2012-05-21

申请人： Fuchen Mu ,  Paul A Bogucki ,  Chen He

发明人： Fuchen Mu ,  Paul A Bogucki ,  Chen He

IPC分类号： G11C11/34 ,  G11C29/50

CPC分类号： G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

摘要： A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.

摘要翻译： 用于检测非易失性存储器的泄漏位的技术包括擦除非易失性存储器的单元。 在擦除之后，对单元施加偏压应力。 在向单元施加偏置应力之后对单元执行擦除验证操作。 最后，基于各个单元的阈值电压是否低于擦除验证电平，确定单元是否通过或者失败擦除验证操作。

公开(公告)号：US20150023106A1

公开(公告)日：2015-01-22

申请号：US13942814

申请日：2013-07-16

申请人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

发明人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C16/16

摘要： Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.

摘要翻译： 公开了用于NVM系统内的非易失性存储器（NVM）单元的自适应擦除恢复的方法和系统。 自适应擦除恢复实施例基于被擦除的NVM块的大小和操作温度自适应地调整擦除恢复放电速率和/或放电时间。 在一个示例性实施例中，通过调节在放电电路内使能的放电晶体管的数量来调整擦除恢复放电率，从而调节用于擦除恢复的放电电流。 查找表用于存储与要恢复的NVM块大小相关联的擦除恢复放电率和/或放电时间和/或工作温度。 通过自适应地控制擦除恢复放电率和/或时间，所公开的实施例提高了宽范围NVM块大小的整体擦除性能，同时避免了对NVM系统内的高电压电路的可能损坏。

公开(公告)号：US08873316B2

公开(公告)日：2014-10-28

申请号：US13557481

申请日：2012-07-25

申请人： Fuchen Mu ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C7/00

CPC分类号： G11C16/12 ,  G11C29/021 ,  G11C29/028

摘要： Methods and systems are disclosed for making temperature-based adjustments to bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store temperature-based bias condition information in storage circuitry. The disclosed embodiments select and apply bias conditions for the NVM cells based upon temperature measurements.

摘要翻译： 公开了用于对非易失性存储器（NVM）单元的偏置条件进行基于温度的调整以提高NVM系统的性能和产品寿命的方法和系统。 系统实施例包括具有NVM控制器，偏置电压发生器和NVM单元阵列的集成NVM系统。 此外，NVM系统可以将基于温度的偏置条件信息存储在存储电路中。 所公开的实施例基于温度测量来选择和应用NVM单元的偏置条件。

公开(公告)号：US20140029335A1

公开(公告)日：2014-01-30

申请号：US13557481

申请日：2012-07-25

申请人： Fuchen Mu ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C16/06

CPC分类号： G11C16/12 ,  G11C29/021 ,  G11C29/028

摘要： Methods and systems are disclosed for making temperature-based adjustments to bias conditions for non-volatile memory (NVM) cells to improve performance and product lifetime of NVM systems. System embodiments include integrated NVM systems having an NVM controller, a bias voltage generator, and an NVM cell array. Further, the NVM systems can store temperature-based bias condition information in storage circuitry. The disclosed embodiments select and apply bias conditions for the NVM cells based upon temperature measurements.

摘要翻译： 公开了用于对非易失性存储器（NVM）单元的偏置条件进行基于温度的调整以提高NVM系统的性能和产品寿命的方法和系统。 系统实施例包括具有NVM控制器，偏置电压发生器和NVM单元阵列的集成NVM系统。 此外，NVM系统可以将基于温度的偏置条件信息存储在存储电路中。 所公开的实施例基于温度测量来选择和应用NVM单元的偏置条件。

公开(公告)号：US20090231925A1

公开(公告)日：2009-09-17

申请号：US12048683

申请日：2008-03-14

申请人： Fuchen Mu ,  Marco A. Cabassi ,  Ronald J. Syzdek

发明人： Fuchen Mu ,  Marco A. Cabassi ,  Ronald J. Syzdek

IPC分类号： G11C16/06 ,  G11C16/26

CPC分类号： G11C16/28 ,  G11C7/14 ,  G11C11/5642

摘要： A set of reference cells is used for sensing the data values stored at bit cells of a memory device. In response to an event, the reference cell providing the highest output of the set is selected as the reference cell to be used for subsequent memory access operations. The remaining reference cells are disabled so that they can recover back to or near their original non-degraded states. At each successive event, the set of reference cells can be reassessed to identify the reference cell that provides the highest output at that time and the memory device can be reconfigured to utilize the reference cell so identified. By utilizing the reference cell having the highest output to provide the read reference and disabling the remaining reference cells, the likelihood of the read reference falling below a minimum threshold can be reduced.

摘要翻译： 一组参考单元用于感测存储在存储器件的位单元中的数据值。 响应于事件，提供集合的最高输出的参考单元被选择为用于后续存储器存取操作的参考单元。 剩余的参考单元被禁用，使得它们可以恢复到其原始非退化状态或其附近。 在每个连续事件中，可以重新评估参考单元集合以识别在该时间提供最高输出的参考单元，并且可重新配置存储器件以利用如此识别的参考单元。 通过利用具有最高输出的参考单元来提供读取参考并禁用剩余的参考单元，可以减少低于最小阈值的读取参考的可能性。

公开(公告)号：US20150085593A1

公开(公告)日：2015-03-26

申请号：US14033622

申请日：2013-09-23

申请人： FUCHEN MU ,  Chen He ,  Yanzhuo Wang

发明人： FUCHEN MU ,  Chen He ,  Yanzhuo Wang

IPC分类号： G11C7/08

CPC分类号： G11C7/08 ,  G11C7/14 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3459 ,  G11C16/349

摘要： A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation.

摘要翻译： 感测放大器被配置为感测来自非易失性存储器阵列的选定位单元的电流，并将感测的电流与参考电流进行比较，以确定存储在位单元中的逻辑状态。 控制器被配置为在存储器阵列的至少一部分上执行编程/擦除操作以改变存储器阵列的该部分的至少一个比特单元的逻辑状态; 确定在编程/擦除操作期间施加到至少一个位单元的编程/擦除脉冲的数量，以实现逻辑状态的改变; 并且当编程/擦除脉冲的数量超过脉冲计数阈值时，调整读出放大器的参考电流以用于随后的编程/擦除操作。

公开(公告)号：US20140063946A1

公开(公告)日：2014-03-06

申请号：US13596764

申请日：2012-08-28

申请人： FUCHEN MU ,  Yanzhuo Wang

发明人： FUCHEN MU ,  Yanzhuo Wang

IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/04

CPC分类号： G11C16/3468

摘要： A semiconductor memory device comprises a memory controller, and an array of memory cells coupled to communicate with the memory controller. The memory controller is configured to perform a first soft program operation using first soft program voltages and a first soft program verify level, and determine whether a first charge trapping threshold has been reached. When the first charge trapping threshold has been reached, a second soft program operation is performed using second soft program voltages and a second soft program verify level.

摘要翻译： 半导体存储器件包括存储器控制器和耦合以与存储器控制器通信的存储器单元的阵列。 存储器控制器被配置为使用第一软编程电压和第一软程序验证电平来执行第一软编程操作，并且确定是否已经达到第一电荷捕获阈值。 当达到第一电荷捕获阈值时，使用第二软编程电压和第二软程序验证电平来执行第二软编程操作。

公开(公告)号：US20130308402A1

公开(公告)日：2013-11-21

申请号：US13476711

申请日：2012-05-21

申请人： Fuchen Mu ,  Paul A. Bogucki ,  Chen He

发明人： Fuchen Mu ,  Paul A. Bogucki ,  Chen He

IPC分类号： G11C29/04

CPC分类号： G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

摘要： A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.

摘要翻译： 用于检测非易失性存储器的泄漏位的技术包括擦除非易失性存储器的单元。 在擦除之后，对单元施加偏压应力。 在向单元施加偏置应力之后对单元执行擦除验证操作。 最后，基于各个单元的阈值电压是否低于擦除验证电平，确定单元是否通过或者失败擦除验证操作。

公开(公告)号：US20130194874A1

公开(公告)日：2013-08-01

申请号：US13755606

申请日：2013-01-31

申请人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C16/3404 ,  G11C16/349

摘要： Methods and systems are disclosed for dynamic healing of non-volatile memory (NVM) cells within NVM systems. The dynamic healing embodiments described herein relax damage within tunnel dielectric layers for NVM cells that occurs over time from charges (e.g., holes and/or electrons) becoming trapped within these tunnel dielectric layers. NVM operations with respect to which dynamic healing processes can be applied include, for example, erase operations, program operations, and read operations. For example, dynamic healing can be applied where performance for the NVM system degrades beyond a selected performance level for an NVM operation, such as elevated erase/program pulse counts for erase/program operations and bit errors for read operations. A variety of healing techniques can be applied, such as drain stress processes, gate stress processes, and/or other desired healing techniques.

摘要翻译： 公开了用于NVM系统内的非易失性存储器（NVM）单元的动态愈合的方法和系统。 本文描述的动态愈合实施例在电荷（例如，空穴和/或电子）被俘获在这些隧道电介质层内的时间内，随着时间的推移而在NVM电池的隧道电介质层内松弛损伤。 关于可以应用哪些动态恢复过程的NVM操作包括例如擦除操作，程序操作和读取操作。 例如，在NVM系统的性能下降到NVM操作的选定性能水平之外，例如擦除/编程操作的擦除/编程脉冲计数升高以及读取操作的位错误，可以应用动态恢复。 可以应用各种愈合技术，例如排水应力过程，门应力过程和/或其他所需的愈合技术。