公开(公告)号：US20130308402A1

公开(公告)日：2013-11-21

申请号：US13476711

申请日：2012-05-21

申请人： Fuchen Mu ,  Paul A. Bogucki ,  Chen He

发明人： Fuchen Mu ,  Paul A. Bogucki ,  Chen He

IPC分类号： G11C29/04

CPC分类号： G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

摘要： A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.

摘要翻译： 用于检测非易失性存储器的泄漏位的技术包括擦除非易失性存储器的单元。 在擦除之后，对单元施加偏压应力。 在向单元施加偏置应力之后对单元执行擦除验证操作。 最后，基于各个单元的阈值电压是否低于擦除验证电平，确定单元是否通过或者失败擦除验证操作。

公开(公告)号：US08995202B2

公开(公告)日：2015-03-31

申请号：US13476711

申请日：2012-05-21

申请人： Fuchen Mu ,  Paul A Bogucki ,  Chen He

发明人： Fuchen Mu ,  Paul A Bogucki ,  Chen He

IPC分类号： G11C11/34 ,  G11C29/50

CPC分类号： G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

摘要： A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.

摘要翻译： 用于检测非易失性存储器的泄漏位的技术包括擦除非易失性存储器的单元。 在擦除之后，对单元施加偏压应力。 在向单元施加偏置应力之后对单元执行擦除验证操作。 最后，基于各个单元的阈值电压是否低于擦除验证电平，确定单元是否通过或者失败擦除验证操作。

公开(公告)号：US20130194874A1

公开(公告)日：2013-08-01

申请号：US13755606

申请日：2013-01-31

申请人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C16/3404 ,  G11C16/349

摘要： Methods and systems are disclosed for dynamic healing of non-volatile memory (NVM) cells within NVM systems. The dynamic healing embodiments described herein relax damage within tunnel dielectric layers for NVM cells that occurs over time from charges (e.g., holes and/or electrons) becoming trapped within these tunnel dielectric layers. NVM operations with respect to which dynamic healing processes can be applied include, for example, erase operations, program operations, and read operations. For example, dynamic healing can be applied where performance for the NVM system degrades beyond a selected performance level for an NVM operation, such as elevated erase/program pulse counts for erase/program operations and bit errors for read operations. A variety of healing techniques can be applied, such as drain stress processes, gate stress processes, and/or other desired healing techniques.

摘要翻译： 公开了用于NVM系统内的非易失性存储器（NVM）单元的动态愈合的方法和系统。 本文描述的动态愈合实施例在电荷（例如，空穴和/或电子）被俘获在这些隧道电介质层内的时间内，随着时间的推移而在NVM电池的隧道电介质层内松弛损伤。 关于可以应用哪些动态恢复过程的NVM操作包括例如擦除操作，程序操作和读取操作。 例如，在NVM系统的性能下降到NVM操作的选定性能水平之外，例如擦除/编程操作的擦除/编程脉冲计数升高以及读取操作的位错误，可以应用动态恢复。 可以应用各种愈合技术，例如排水应力过程，门应力过程和/或其他所需的愈合技术。

公开(公告)号：US20150023106A1

公开(公告)日：2015-01-22

申请号：US13942814

申请日：2013-07-16

申请人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

发明人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C16/16

摘要： Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.

摘要翻译： 公开了用于NVM系统内的非易失性存储器（NVM）单元的自适应擦除恢复的方法和系统。 自适应擦除恢复实施例基于被擦除的NVM块的大小和操作温度自适应地调整擦除恢复放电速率和/或放电时间。 在一个示例性实施例中，通过调节在放电电路内使能的放电晶体管的数量来调整擦除恢复放电率，从而调节用于擦除恢复的放电电流。 查找表用于存储与要恢复的NVM块大小相关联的擦除恢复放电率和/或放电时间和/或工作温度。 通过自适应地控制擦除恢复放电率和/或时间，所公开的实施例提高了宽范围NVM块大小的整体擦除性能，同时避免了对NVM系统内的高电压电路的可能损坏。

公开(公告)号：US09030883B2

公开(公告)日：2015-05-12

申请号：US13942814

申请日：2013-07-16

申请人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

发明人： Chen He ,  Yanzhuo Wang ,  Fuchen Mu

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/06 ,  G11C7/04 ,  G11C16/16

摘要： Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.

摘要翻译： 公开了用于NVM系统内的非易失性存储器（NVM）单元的自适应擦除恢复的方法和系统。 自适应擦除恢复实施例基于被擦除的NVM块的大小和操作温度自适应地调整擦除恢复放电速率和/或放电时间。 在一个示例性实施例中，通过调节在放电电路内使能的放电晶体管的数量来调整擦除恢复放电率，从而调节用于擦除恢复的放电电流。 查找表用于存储与要恢复的NVM块大小相关联的擦除恢复放电率和/或放电时间和/或工作温度。 通过自适应地控制擦除恢复放电率和/或时间，所公开的实施例提高了宽范围NVM块大小的整体擦除性能，同时避免了对NVM系统内的高电压电路的可能损坏。

公开(公告)号：US20150117112A1

公开(公告)日：2015-04-30

申请号：US14069195

申请日：2013-10-31

申请人： CHEN HE ,  Fuchen Mu ,  Yanzhuo Wang

发明人： CHEN HE ,  Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C16/16 ,  G11C16/34

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/14 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345

摘要： A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.

摘要翻译： 一种方法包括擦除其中块内的存储单元被同时擦除的多个存储单元块。 使用多次施加的擦除脉冲来执行多个块中的每个块的擦除。 擦除脉冲并行地施加到多个块。 在每次施加擦除脉冲之后执行擦除验证。 在擦除脉冲的数字应用之后，确定包括任何存储器单元组成的组之一的条件是否已经比第一预定量更多地被擦除，并且已经擦除了小于第二预定量的任何存储单元已被擦除 。 如果满足条件，则通过将擦除脉冲施加到具有独立于多个块的其他块的条件的具有存储器单元的块来继续擦除。

公开(公告)号：US20140204678A1

公开(公告)日：2014-07-24

申请号：US13747504

申请日：2013-01-23

申请人： Fuchen Mu ,  Chen He

发明人： Fuchen Mu ,  Chen He

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/3409 ,  G11C16/349

摘要： A method and apparatus for detecting a latent slow bit (e.g., a latent slow-to-erase bit) in a non-volatile memory (NVM) is disclosed. A maximum number of soft program pulses among addresses during an erase cycle is counted. In accordance with at least one embodiment, a number of erase pulses during the erase cycle is counted. In accordance with various embodiments, determinations are made as to whether the maximum number of the soft program pulses has increased at a rate of at least a predetermined minimum rate comparing to a previous erase cycle, whether the maximum number of the soft program pulses has exceeded a predetermined threshold, whether the number of erase pulses has increased comparing to a previous erase cycle, or combinations thereof. In response to such determinations, the NVM is either passed or failed on the basis of the absence or presence of a slow bit in the NVM.

摘要翻译： 公开了一种用于检测非易失性存储器（NVM）中的潜在慢位（例如，潜在慢擦除位）的方法和装置。 对擦除周期内的地址间的软编程脉冲的最大数进行计数。 根据至少一个实施例，对擦除周期期间的擦除脉冲进行计数。 根据各种实施例，确定最大数量的软编程脉冲是否以与先前擦除周期相比至少预定最小速率的速率增加，无论最大数量的软编程脉冲是否已经超过 预定阈值，擦除脉冲的数目是否与先前的擦除周期相比增加，或其组合。 响应于这样的确定，NVM将根据NVM中不存在或存在慢速位而通过或失败。

公开(公告)号：US08713406B2

公开(公告)日：2014-04-29

申请号：US13459344

申请日：2012-04-30

申请人： Fuchen Mu ,  Frank K. Baker, Jr. ,  Chen He

发明人： Fuchen Mu ,  Frank K. Baker, Jr. ,  Chen He

IPC分类号： G11C29/00

CPC分类号： G11C16/16 ,  G11C16/3481

摘要： A method of erasing a non-volatile semiconductor memory device comprising determining a number of bit cells that failed to erase verify during an erase operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further comprises determining whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The erase operation is considered successful if the number of bit cells that failed to erase verify after a predetermined number of erase pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells.

摘要翻译： 一种擦除非易失性半导体存储器件的方法，包括在擦除操作期间确定不能擦除验证的位单元数目。 位单元包括在位单元阵列中的位单元的子集中。 该方法还包括确定是否先前对位单元的子集执行纠错码（ECC）校正。 如果在预定数量的擦除脉冲之后无法擦除验证的比特单元的数量低于阈值并且还没有对比特单元的子集执行ECC校正，则擦除操作被认为是成功的。

公开(公告)号：US09082493B2

公开(公告)日：2015-07-14

申请号：US14069195

申请日：2013-10-31

申请人： Chen He ,  Fuchen Mu ,  Yanzhuo Wang

发明人： Chen He ,  Fuchen Mu ,  Yanzhuo Wang

IPC分类号： G11C11/34 ,  G11C16/16 ,  G11C16/34 ,  G11C16/14 ,  G11C11/56

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/14 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345

摘要： A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.

摘要翻译： 一种方法包括擦除其中块内的存储单元被同时擦除的多个存储单元块。 使用多次施加的擦除脉冲来执行多个块中的每个块的擦除。 擦除脉冲并行地施加到多个块。 在每次施加擦除脉冲之后执行擦除验证。 在擦除脉冲的数字应用之后，确定包括任何存储器单元组成的组之一的条件是否已经比第一预定量更多地被擦除，并且已经擦除了小于第二预定量的任何存储单元已被擦除 。 如果满足条件，则通过将擦除脉冲施加到具有独立于多个块的其他块的条件的具有存储器单元的块来继续擦除。

公开(公告)号：US20150049555A1

公开(公告)日：2015-02-19

申请号：US13965731

申请日：2013-08-13

申请人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

发明人： Fuchen Mu ,  Chen He ,  Yanzhuo Wang

IPC分类号： G11C16/34 ,  G11C16/14

CPC分类号： G11C16/3459 ,  G11C16/14 ,  G11C16/345

摘要： Methods and systems are disclosed for extended erase protection for non-volatile memory (NVM) cells during embedded erase operations for NVM systems. The embodiments described herein utilize an additional threshold voltage (Vt) check after soft programming operation within an embedded erase operation completes to provide extended erase protection of NVM cells. In particular, the threshold voltages for NVM cells are compared against a threshold voltage (Vt) check voltage (VCHK) level and an additional embedded erase cycle is performed if any NVM cells are found to exceed the threshold voltage (Vt) check voltage (VCHK) level. The threshold voltage (Vt) check voltage (VCHK) level can be, for example, a voltage level that is slightly higher than an erase verify voltage (VEV) level and lower than read voltage level (VR).

摘要翻译： 公开了用于NVM系统的嵌入式擦除操作期间用于非易失性存储器（NVM）单元的扩展擦除保护的方法和系统。 本文描述的实施例在嵌入式擦除操作中的软编程操作完成之后利用额外的阈值电压（Vt）检查，以提供NVM单元的扩展擦除保护。 特别地，NVM单元的阈值电压与阈值电压（Vt）检查电压（VCHK）电平进行比较，并且如果发现任何NVM单元超过阈值电压（Vt）检查电压（VCHK），执行附加的嵌入式擦除周期 ）级别。 阈值电压（Vt）检查电压（VCHK）电平可以是例如略高于擦除验证电压（VEV）电平并低于读取电压电平（VR）的电压电平。