Low voltage detector
    1.
    发明授权
    Low voltage detector 有权
    低电压检测器

    公开(公告)号:US08896349B2

    公开(公告)日:2014-11-25

    申请号:US13161954

    申请日:2011-06-16

    IPC分类号: H03K5/153

    摘要: A low voltage detector (100) includes a power supply voltage monitor circuit (110) that produces a voltage VSP related to a first a power supply voltage, and a voltage generator (105), which includes a plurality of self-cascode MOSFET (SCM) structures (101-103) in a cascade configuration, that generates a reference voltage Vxm. A voltage comparator (140) outputs an output signal in response to a differential between Vxm and VSP, wherein Vxm and VSP have proportional to absolute temperature behavior (PTAT) over temperature with respect to a second power supply voltage. The output signal changes state when the first power supply voltage equals a trip point of the comparator. Each SCM structure is sized to provide a rate of change with temperature of the PTAT behavior of Vxm that matches a rate of change with temperature of the PTAT behavior of VSP.

    摘要翻译: 低电压检测器(100)包括产生与第一电源电压相关的电压VSP的电源电压监视电路(110),以及电压发生器(105),其包括多个自共源共栅MOSFET(SCM )结构(101-103),其产生参考电压Vxm。 电压比较器(140)响应于Vxm和VSP之间的差分输出输出信号,其中Vxm和VSP与温度相对于第二电源电压的绝对温度特性(PTAT)成比例。 当第一电源电压等于比较器的跳变点时,输出信号改变状态。 每个SCM结构的大小可以提供与VMI的PTAT行为的温度的变化率,其与VSP的PTAT行为的温度的变化率匹配。

    Process of forming an electronic device including a resistor-capacitor filter
    2.
    发明授权
    Process of forming an electronic device including a resistor-capacitor filter 有权
    形成包括电阻 - 电容滤波器的电子器件的工艺

    公开(公告)号:US08017474B2

    公开(公告)日:2011-09-13

    申请号:US12133992

    申请日:2008-06-05

    IPC分类号: H01L29/94

    摘要: A process of forming an electronic device can include forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material, forming a gate dielectric layer over a substrate, forming a capacitor electrode over the capacitor dielectric layer, forming a gate electrode over the gate dielectric layer, and forming an input terminal and an output terminal to the capacitor electrode. The input terminal and the output terminal can be spaced apart from each other and are connected to different components within the electronic device. A filter can include the base region, the capacitor dielectric layer, and the capacitor electrode. A transistor structure can include the gate dielectric layer and the gate electrode. An electronic device can include a low-pass filter and a transistor structure, such as an n-channel transistor or a p-channel transistor.

    摘要翻译: 形成电子器件的工艺可以包括在基极区域上形成电容器电介质层,其中基极区域包括基底半导体材料,在衬底上形成栅极电介质层,在电容器电介质层上形成电容器电极, 栅极电极,并且形成输入端子和输出端子到电容器电极。 输入端子和输出端子可以彼此间隔开并且连接到电子设备内的不同部件。 滤波器可以包括基极区域,电容器介电层和电容器电极。 晶体管结构可以包括栅极电介质层和栅电极。 电子器件可以包括低通滤波器和诸如n沟道晶体管或p沟道晶体管的晶体管结构。

    LOW VOLTAGE DETECTOR
    3.
    发明申请
    LOW VOLTAGE DETECTOR 有权
    低电压检测器

    公开(公告)号:US20120323508A1

    公开(公告)日:2012-12-20

    申请号:US13161954

    申请日:2011-06-16

    IPC分类号: G06F19/00 G01R21/14 G01R19/00

    摘要: A low voltage detector (100) includes a power supply voltage monitor circuit (110) that produces a voltage VSP related to a first a power supply voltage, and a voltage generator (105), which includes a plurality of self-cascode MOSFET (SCM) structures (101-103) in a cascade configuration, that generates a reference voltage Vxm. A voltage comparator (140) outputs an output signal in response to a differential between Vxm and VSP, wherein Vxm and VSP have proportional to absolute temperature behavior (PTAT) over temperature with respect to a second power supply voltage. The output signal changes state when the first power supply voltage equals a trip point of the comparator. Each SCM structure is sized to provide a rate of change with temperature of the PTAT behavior of Vxm that matches a rate of change with temperature of the PTAT behavior of VSP.

    摘要翻译: 低电压检测器(100)包括产生与第一电源电压相关的电压VSP的电源电压监视电路(110)和包括多个自共源共栅MOSFET(SCM)的电压发生器(105) )结构(101-103),其产生参考电压Vxm。 电压比较器(140)响应于Vxm和VSP之间的差分输出输出信号,其中Vxm和VSP与温度相对于第二电源电压的绝对温度特性(PTAT)成比例。 当第一电源电压等于比较器的跳变点时,输出信号改变状态。 每个SCM结构的大小可以提供与VMI的PTAT行为的温度的变化率,其与VSP的PTAT行为的温度的变化率匹配。

    ELECTRONIC DEVICE INCLUDING A RESISTOR-CAPACITOR FILTER AND A PROCESS OF FORMING THE SAME
    4.
    发明申请
    ELECTRONIC DEVICE INCLUDING A RESISTOR-CAPACITOR FILTER AND A PROCESS OF FORMING THE SAME 有权
    包括电容电容滤波器的电子器件及其形成方法

    公开(公告)号:US20090302364A1

    公开(公告)日:2009-12-10

    申请号:US12133992

    申请日:2008-06-05

    摘要: A process of forming an electronic device can include forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material, forming a gate dielectric layer over a substrate, forming a capacitor electrode over the capacitor dielectric layer, forming a gate electrode over the gate dielectric layer, and forming an input terminal and an output terminal to the capacitor electrode. The input terminal and the output terminal can be spaced apart from each other and are connected to different components within the electronic device. A filter can include the base region, the capacitor dielectric layer, and the capacitor electrode. A transistor structure can include the gate dielectric layer and the gate electrode. An electronic device can include a low-pass filter and a transistor structure, such as an n-channel transistor or a p-channel transistor.

    摘要翻译: 形成电子器件的工艺可以包括在基极区域上形成电容器电介质层,其中基极区域包括基底半导体材料,在衬底上形成栅极电介质层,在电容器电介质层上形成电容器电极, 栅极电极,并且形成输入端子和输出端子到电容器电极。 输入端子和输出端子可以彼此间隔开并且连接到电子设备内的不同部件。 滤波器可以包括基极区域,电容器介电层和电容器电极。 晶体管结构可以包括栅极电介质层和栅电极。 电子器件可以包括低通滤波器和诸如n沟道晶体管或p沟道晶体管的晶体管结构。

    PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A RESISTOR-CAPACITOR FILTER
    5.
    发明申请
    PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A RESISTOR-CAPACITOR FILTER 有权
    形成包括电容电容滤波器的电子器件的方法

    公开(公告)号:US20110309419A1

    公开(公告)日:2011-12-22

    申请号:US13223573

    申请日:2011-09-01

    IPC分类号: H01L27/06

    摘要: A process of forming an electronic device can include forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material, forming a gate dielectric layer over a substrate, forming a capacitor electrode over the capacitor dielectric layer, forming a gate electrode over the gate dielectric layer, and forming an input terminal and an output terminal to the capacitor electrode. The input terminal and the output terminal can be spaced apart from each other and are connected to different components within the electronic device. A filter can include the base region, the capacitor dielectric layer, and the capacitor electrode. A transistor structure can include the gate dielectric layer and the gate electrode. An electronic device can include a low-pass filter and a transistor structure, such as an n-channel transistor or a p-channel transistor.

    摘要翻译: 形成电子器件的工艺可以包括在基极区域上形成电容器电介质层,其中基极区域包括基底半导体材料,在衬底上形成栅极电介质层,在电容器电介质层上形成电容器电极, 栅极电极,并且形成输入端子和输出端子到电容器电极。 输入端子和输出端子可以彼此间隔开并且连接到电子设备内的不同部件。 滤波器可以包括基极区域,电容器介电层和电容器电极。 晶体管结构可以包括栅极电介质层和栅电极。 电子器件可以包括低通滤波器和诸如n沟道晶体管或p沟道晶体管的晶体管结构。

    Current-mode memory cell
    6.
    发明授权
    Current-mode memory cell 有权
    电流模式存储单元

    公开(公告)号:US07495987B2

    公开(公告)日:2009-02-24

    申请号:US11811547

    申请日:2007-06-11

    IPC分类号: G11C17/18

    CPC分类号: G11C17/18 G11C17/16

    摘要: Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the second current source is coupled to the first reference through a programmable fuse. A third current is sunk from the summing node with a current sink, wherein the current sink is coupled to a second reference, and wherein a third current limit is greater than a first current limit and less than the sum of the first current limit and the second current limit. A voltage at the summing node is output in response to the first current, the second current, and the third current. The first and second current sources, and the current sink can be current mirrors.

    摘要翻译: 用于读取存储器单元的方法和相应的系统包括从第一电流源进入求和节点的第一电流,其中第一电流源耦合到第一参考。 第二电流源自第二电流源到求和节点,其中第二电流源通过可编程保险丝耦合到第一参考。 第三电流从具有电流吸收器的求和节点沉没,其中电流吸收器耦合到第二参考,并且其中第三电流限制大于第一电流限制并且小于第一电流限制和 第二电流限制。 响应于第一电流,第二电流和第三电流输出求和节点处的电压。 第一和第二电流源,以及电流源可以是电流镜。

    Switched-capacitor amplifier circuit
    7.
    发明授权
    Switched-capacitor amplifier circuit 有权
    开关电容放大器电路

    公开(公告)号:US08198937B1

    公开(公告)日:2012-06-12

    申请号:US13048113

    申请日:2011-03-15

    IPC分类号: H03F1/02

    摘要: A switched-capacitor amplifier circuit (200 and 300) with rail-to-rail capability without requiring a rail-to-rail operational amplifier includes a switched-capacitor amplifier (202 and 302) and an input network (201) coupled to the switched-capacitor amplifier. The switched-capacitor amplifier includes a non-rail-to-rail operational amplifier (275 and 375). The input network prevents the non-rail-to-rail operational amplifier from receiving an input differential signal that has a common-mode voltage at or near rails of the non-rail-to-rail operational amplifier. Voltages at input terminals of the operational amplifier remain near analog ground, which is an arbitrary voltage level between the rails, during both phases of switching in the switched-capacitor amplifier. In one embodiment, the switched-capacitor amplifier uses a correlated double sampling technique.

    摘要翻译: 具有轨到轨能力而不需要轨到轨运算放大器的开关电容放大器电路(200和300)包括开关电容放大器(202和302)和耦合到开关电容器的输入网络(201) 电容放大器。 开关电容放大器包括非轨到轨运算放大器(275和375)。 输入网络防止非轨到轨运算放大器接收在非轨至轨运算放大器的轨道处或其附近具有共模电压的输入差分信号。 在开关电容放大器的开关的两个阶段期间,运算放大器的输入端子处的电压保持靠近模拟地,这是导轨之间的任意电压电平。 在一个实施例中,开关电容放大器使用相关双重采样技术。

    Current-mode memory cell
    8.
    发明申请
    Current-mode memory cell 有权
    电流模式存储单元

    公开(公告)号:US20080304348A1

    公开(公告)日:2008-12-11

    申请号:US11811547

    申请日:2007-06-11

    IPC分类号: G11C17/16

    CPC分类号: G11C17/18 G11C17/16

    摘要: Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the second current source is coupled to the first reference through a programmable fuse. A third current is sunk from the summing node with a current sink, wherein the current sink is coupled to a second reference, and wherein a third current limit is greater than a first current limit and less than the sum of the first current limit and the second current limit. A voltage at the summing node is output in response to the first current, the second current, and the third current. The first and second current sources, and the current sink can be current mirrors.

    摘要翻译: 用于读取存储器单元的方法和相应的系统包括从第一电流源进入求和节点的第一电流,其中第一电流源耦合到第一参考。 第二电流源自第二电流源到求和节点,其中第二电流源通过可编程保险丝耦合到第一参考。 第三电流从具有电流吸收器的求和节点沉没,其中电流吸收器耦合到第二参考,并且其中第三电流限制大于第一电流限制并且小于第一电流限制和 第二电流限制。 响应于第一电流,第二电流和第三电流输出求和节点处的电压。 第一和第二电流源,以及电流源可以是电流镜。

    Process of forming an electronic device including a resistor-capacitor filter
    9.
    发明授权
    Process of forming an electronic device including a resistor-capacitor filter 有权
    形成包括电阻 - 电容滤波器的电子器件的工艺

    公开(公告)号:US08629530B2

    公开(公告)日:2014-01-14

    申请号:US13223573

    申请日:2011-09-01

    IPC分类号: H01L27/06

    摘要: A process of forming an electronic device can include forming a capacitor dielectric layer over a base region, wherein the base region includes a base semiconductor material, forming a gate dielectric layer over a substrate, forming a capacitor electrode over the capacitor dielectric layer, forming a gate electrode over the gate dielectric layer, and forming an input terminal and an output terminal to the capacitor electrode. The input terminal and the output terminal can be spaced apart from each other and are connected to different components within the electronic device. A filter can include the base region, the capacitor dielectric layer, and the capacitor electrode. A transistor structure can include the gate dielectric layer and the gate electrode. An electronic device can include a low-pass filter and a transistor structure, such as an n-channel transistor or a p-channel transistor.

    摘要翻译: 形成电子器件的工艺可以包括在基极区域上形成电容器电介质层,其中基极区域包括基底半导体材料,在衬底上形成栅极电介质层,在电容器电介质层上形成电容器电极, 栅极电极,并且形成输入端子和输出端子到电容器电极。 输入端子和输出端子可以彼此间隔开并且连接到电子设备内的不同部件。 滤波器可以包括基极区域,电容器介电层和电容器电极。 晶体管结构可以包括栅极电介质层和栅电极。 电子器件可以包括低通滤波器和诸如n沟道晶体管或p沟道晶体管的晶体管结构。

    Low voltage detector
    10.
    发明授权
    Low voltage detector 有权
    低电压检测器

    公开(公告)号:US08330526B2

    公开(公告)日:2012-12-11

    申请号:US12836997

    申请日:2010-07-15

    IPC分类号: H01L35/00 H03K5/22

    CPC分类号: G06F1/28 G01R19/16552

    摘要: A low voltage detector (100) includes a voltage and current reference circuit (102); a power supply voltage monitor circuit (104), coupled to the voltage and current reference circuit and to a power supply; and a voltage comparator (106), coupled to the voltage and current reference circuit and to the power supply voltage monitor circuit. The voltage and current reference circuit includes a self-cascode MOSFET structure (SCM) (110) that produces a reference voltage. The power supply voltage monitoring circuit includes another SCM (140) that produces a monitor voltage, related to the power supply voltage. The reference voltage and the monitor voltage have a same behavior with changes in temperature, thereby allowing the trip point of the low voltage detector to minimally vary with temperature. The low voltage detector is disposed on an integrated circuit (101), and the transistors of the low voltage detector consist of only CMOS transistors.

    摘要翻译: 低电压检测器(100)包括电压和电流参考电路(102); 电源电压监视电路(104),耦合到电压和电流参考电路和电源; 以及耦合到电压和电流参考电路和电源电压监视电路的电压比较器(106)。 电压和电流参考电路包括产生参考电压的自共源共栅MOSFET结构(SCM)(110)。 电源电压监视电路包括产生与电源电压相关的监视电压的另一SCM(140)。 参考电压和监视电压与温度变化具有相同的行为,从而允许低电压检测器的跳变点最小化随温度变化。 低电压检测器设置在集成电路(101)上,低电压检测器的晶体管仅由CMOS晶体管构成。