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公开(公告)号：US08198937B1
公开(公告)日：2012-06-12
申请号：US13048113
申请日：2011-03-15
IPC分类号： H03F1/02
CPC分类号： H03F3/45475 , H03F2200/81 , H03F2203/45514 , H03F2203/45551
摘要： A switched-capacitor amplifier circuit (200 and 300) with rail-to-rail capability without requiring a rail-to-rail operational amplifier includes a switched-capacitor amplifier (202 and 302) and an input network (201) coupled to the switched-capacitor amplifier. The switched-capacitor amplifier includes a non-rail-to-rail operational amplifier (275 and 375). The input network prevents the non-rail-to-rail operational amplifier from receiving an input differential signal that has a common-mode voltage at or near rails of the non-rail-to-rail operational amplifier. Voltages at input terminals of the operational amplifier remain near analog ground, which is an arbitrary voltage level between the rails, during both phases of switching in the switched-capacitor amplifier. In one embodiment, the switched-capacitor amplifier uses a correlated double sampling technique.
摘要翻译： 具有轨到轨能力而不需要轨到轨运算放大器的开关电容放大器电路（200和300）包括开关电容放大器（202和302）和耦合到开关电容器的输入网络（201） 电容放大器。 开关电容放大器包括非轨到轨运算放大器（275和375）。 输入网络防止非轨到轨运算放大器接收在非轨至轨运算放大器的轨道处或其附近具有共模电压的输入差分信号。 在开关电容放大器的开关的两个阶段期间，运算放大器的输入端子处的电压保持靠近模拟地，这是导轨之间的任意电压电平。 在一个实施例中，开关电容放大器使用相关双重采样技术。
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公开(公告)号：US08330526B2
公开(公告)日：2012-12-11
申请号：US12836997
申请日：2010-07-15
CPC分类号： G06F1/28 , G01R19/16552
摘要： A low voltage detector (100) includes a voltage and current reference circuit (102); a power supply voltage monitor circuit (104), coupled to the voltage and current reference circuit and to a power supply; and a voltage comparator (106), coupled to the voltage and current reference circuit and to the power supply voltage monitor circuit. The voltage and current reference circuit includes a self-cascode MOSFET structure (SCM) (110) that produces a reference voltage. The power supply voltage monitoring circuit includes another SCM (140) that produces a monitor voltage, related to the power supply voltage. The reference voltage and the monitor voltage have a same behavior with changes in temperature, thereby allowing the trip point of the low voltage detector to minimally vary with temperature. The low voltage detector is disposed on an integrated circuit (101), and the transistors of the low voltage detector consist of only CMOS transistors.
摘要翻译： 低电压检测器（100）包括电压和电流参考电路（102）; 电源电压监视电路（104），耦合到电压和电流参考电路和电源; 以及耦合到电压和电流参考电路和电源电压监视电路的电压比较器（106）。 电压和电流参考电路包括产生参考电压的自共源共栅MOSFET结构（SCM）（110）。 电源电压监视电路包括产生与电源电压相关的监视电压的另一SCM（140）。 参考电压和监视电压与温度变化具有相同的行为，从而允许低电压检测器的跳变点最小化随温度变化。 低电压检测器设置在集成电路（101）上，低电压检测器的晶体管仅由CMOS晶体管构成。
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公开(公告)号：US20120013365A1
公开(公告)日：2012-01-19
申请号：US12836997
申请日：2010-07-15
IPC分类号： H03K5/153
CPC分类号： G06F1/28 , G01R19/16552
摘要： A low voltage detector (100) includes a voltage and current reference circuit (102); a power supply voltage monitor circuit (104), coupled to the voltage and current reference circuit and to a power supply; and a voltage comparator (106), coupled to the voltage and current reference circuit and to the power supply voltage monitor circuit. The voltage and current reference circuit includes a self-cascode MOSFET structure (SCM) (110) that produces a reference voltage. The power supply voltage monitoring circuit includes another SCM (140) that produces a monitor voltage, related to the power supply voltage. The reference voltage and the monitor voltage have a same behavior with changes in temperature, thereby allowing the trip point of the low voltage detector to minimally vary with temperature. The low voltage detector is disposed on an integrated circuit (101), and the transistors of the low voltage detector consist of only CMOS transistors.
摘要翻译： 低电压检测器（100）包括电压和电流参考电路（102）; 电源电压监视电路（104），耦合到电压和电流参考电路和电源; 以及耦合到电压和电流参考电路和电源电压监视电路的电压比较器（106）。 电压和电流参考电路包括产生参考电压的自共源共栅MOSFET结构（SCM）（110）。 电源电压监视电路包括产生与电源电压相关的监视电压的另一SCM（140）。 参考电压和监视电压与温度变化具有相同的行为，从而允许低电压检测器的跳变点最小化随温度变化。 低电压检测器设置在集成电路（101）上，低电压检测器的晶体管仅由CMOS晶体管构成。
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公开(公告)号：US07495987B2
公开(公告)日：2009-02-24
申请号：US11811547
申请日：2007-06-11
IPC分类号： G11C17/18
摘要： Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the second current source is coupled to the first reference through a programmable fuse. A third current is sunk from the summing node with a current sink, wherein the current sink is coupled to a second reference, and wherein a third current limit is greater than a first current limit and less than the sum of the first current limit and the second current limit. A voltage at the summing node is output in response to the first current, the second current, and the third current. The first and second current sources, and the current sink can be current mirrors.
摘要翻译： 用于读取存储器单元的方法和相应的系统包括从第一电流源进入求和节点的第一电流，其中第一电流源耦合到第一参考。 第二电流源自第二电流源到求和节点，其中第二电流源通过可编程保险丝耦合到第一参考。 第三电流从具有电流吸收器的求和节点沉没，其中电流吸收器耦合到第二参考，并且其中第三电流限制大于第一电流限制并且小于第一电流限制和 第二电流限制。 响应于第一电流，第二电流和第三电流输出求和节点处的电压。 第一和第二电流源，以及电流源可以是电流镜。
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公开(公告)号：US20080304348A1
公开(公告)日：2008-12-11
申请号：US11811547
申请日：2007-06-11
IPC分类号： G11C17/16
摘要： Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the second current source is coupled to the first reference through a programmable fuse. A third current is sunk from the summing node with a current sink, wherein the current sink is coupled to a second reference, and wherein a third current limit is greater than a first current limit and less than the sum of the first current limit and the second current limit. A voltage at the summing node is output in response to the first current, the second current, and the third current. The first and second current sources, and the current sink can be current mirrors.
摘要翻译： 用于读取存储器单元的方法和相应的系统包括从第一电流源进入求和节点的第一电流，其中第一电流源耦合到第一参考。 第二电流源自第二电流源到求和节点，其中第二电流源通过可编程保险丝耦合到第一参考。 第三电流从具有电流吸收器的求和节点沉没，其中电流吸收器耦合到第二参考，并且其中第三电流限制大于第一电流限制并且小于第一电流限制和 第二电流限制。 响应于第一电流，第二电流和第三电流输出求和节点处的电压。 第一和第二电流源，以及电流源可以是电流镜。
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公开(公告)号：US08896349B2
公开(公告)日：2014-11-25
申请号：US13161954
申请日：2011-06-16
IPC分类号： H03K5/153
CPC分类号： G01R19/32 , G01R19/16519 , G01R19/16542 , G01R19/16576
摘要： A low voltage detector (100) includes a power supply voltage monitor circuit (110) that produces a voltage VSP related to a first a power supply voltage, and a voltage generator (105), which includes a plurality of self-cascode MOSFET (SCM) structures (101-103) in a cascade configuration, that generates a reference voltage Vxm. A voltage comparator (140) outputs an output signal in response to a differential between Vxm and VSP, wherein Vxm and VSP have proportional to absolute temperature behavior (PTAT) over temperature with respect to a second power supply voltage. The output signal changes state when the first power supply voltage equals a trip point of the comparator. Each SCM structure is sized to provide a rate of change with temperature of the PTAT behavior of Vxm that matches a rate of change with temperature of the PTAT behavior of VSP.
摘要翻译： 低电压检测器（100）包括产生与第一电源电压相关的电压VSP的电源电压监视电路（110），以及电压发生器（105），其包括多个自共源共栅MOSFET（SCM ）结构（101-103），其产生参考电压Vxm。 电压比较器（140）响应于Vxm和VSP之间的差分输出输出信号，其中Vxm和VSP与温度相对于第二电源电压的绝对温度特性（PTAT）成比例。 当第一电源电压等于比较器的跳变点时，输出信号改变状态。 每个SCM结构的大小可以提供与VMI的PTAT行为的温度的变化率，其与VSP的PTAT行为的温度的变化率匹配。
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7.发明授权Programmable voltage reference with a voltage reference circuit having a self-cascode metal-oxide semiconductor field-effect transistor structure 有权具有电压参考电路的可编程参考电压，具有自共存状态金属氧化物半导体场效应晶体管结构公开(公告)号：US08093880B2
公开(公告)日：2012-01-10
申请号：US12277695
申请日：2008-11-25
IPC分类号： G05F3/08
CPC分类号： G05F3/16
摘要： A programmable voltage reference includes a temperature compensated current source and a voltage reference circuit. The temperature compensated current source includes an output configured to provide a reference current. The voltage reference circuit includes an input coupled to the output of the temperature compensated current source and a reference output. The voltage reference circuit includes a self-cascode metal-oxide semiconductor field-effect transistor structure that includes a first device that is diode-connected and operates in a weak inversion saturation region and a second device that operates in a weak inversion triode region. A length of the second device is selectable. The voltage reference circuit is configured to provide a reference voltage on the reference output based on the reference current.
摘要翻译： 可编程电压基准包括温度补偿电流源和电压参考电路。 温度补偿电流源包括被配置为提供参考电流的输出。 电压参考电路包括耦合到温度补偿电流源的输出和参考输出的输入。 电压参考电路包括自共成共栅型金属氧化物半导体场效应晶体管结构，其包括二极管连接并在弱反相饱和区工作的第一器件和在弱反相三极管区工作的第二器件。 第二装置的长度是可选择的。 电压参考电路被配置为基于参考电流在参考输出上提供参考电压。
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公开(公告)号：US20110121809A1
公开(公告)日：2011-05-26
申请号：US12626321
申请日：2009-11-25
IPC分类号： G05F3/16
CPC分类号： G05F3/262
摘要： A bandgap voltage reference unit on an integrated circuit (101) includes a proportional-to-absolute-temperature (PTAT) current source (100) coupled to a bandgap voltage reference circuit (200) that includes a plurality of self-cascode MOSFET structures (201-204) that are cascaded together to form a PTAT voltage generator (205). The bandgap voltage reference circuit also includes a complementary-to-absolute-temperature (CTAT) device (260). A PTAT voltage from the PTAT voltage generator is added to a CTAT voltage from the CTAT device to produce an output voltage of the bandgap voltage reference unit, such that the output voltage is the bandgap voltage of the integrated circuit and such that the output voltage does not change with temperature.
摘要翻译： 集成电路（101）上的带隙电压参考单元包括耦合到带隙电压参考电路（200）的比例绝对温度（PTAT）电流源（100），该带隙电压参考电路包括多个自共源共栅MOSFET结构 201-204），其级联在一起以形成PTAT电压发生器（205）。 带隙电压参考电路还包括互补绝对温度（CTAT）装置（260）。 来自PTAT电压发生器的PTAT电压被加到来自CTAT装置的CTAT电压，以产生带隙电压参考单元的输出电压，使得输出电压是集成电路的带隙电压，并且使得输出电压 不随温度变化。
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公开(公告)号：US08305068B2
公开(公告)日：2012-11-06
申请号：US12626321
申请日：2009-11-25
IPC分类号： G05F3/16
CPC分类号： G05F3/262
摘要： A bandgap voltage reference unit on an integrated circuit (101) includes a proportional-to-absolute-temperature (PTAT) current source (100) coupled to a bandgap voltage reference circuit (200) that includes a plurality of self-cascode MOSFET structures (201-204) that are cascaded together to form a PTAT voltage generator (205). The bandgap voltage reference circuit also includes a complementary-to-absolute-temperature (CTAT) device (260). A PTAT voltage from the PTAT voltage generator is added to a CTAT voltage from the CTAT device to produce an output voltage of the bandgap voltage reference unit, such that the output voltage is the bandgap voltage of the integrated circuit and such that the output voltage does not change with temperature.
摘要翻译： 集成电路（101）上的带隙电压参考单元包括耦合到带隙电压参考电路（200）的比例绝对温度（PTAT）电流源（100），该带隙电压参考电路包括多个自共源共栅MOSFET结构 201-204），其级联在一起以形成PTAT电压发生器（205）。 带隙电压参考电路还包括互补绝对温度（CTAT）装置（260）。 来自PTAT电压发生器的PTAT电压被加到来自CTAT装置的CTAT电压，以产生带隙电压参考单元的输出电压，使得输出电压是集成电路的带隙电压，并且使得输出电压 温度不变。
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公开(公告)号：US07233539B2
公开(公告)日：2007-06-19
申请号：US11135963
申请日：2005-05-24
IPC分类号： G11C17/18
摘要： A non-volatile memory cell 100 includes a static latch 125 having a first terminal and a second terminal, a first transistor 124 having a first current electrode coupled to said first terminal of said static latch 125 and a fusible element 110 having a first terminal coupled to a second current electrode of the first transistor 125 and a second terminal coupled to a first power supply voltage terminal. In a particular embodiment, the non-volatile memory cell includes a fusible element programming circuit 140 coupled to the first terminal of said fusible element. In another particular embodiment, the non-volatile memory cell includes a cell preset circuit 120 coupled to a control electrode of the first transistor.
摘要翻译： 非易失性存储单元100包括具有第一端子和第二端子的静态锁存器125，第一晶体管124，其具有耦合到所述静态锁存器125的所述第一端子的第一电流电极和可熔元件110，第一端子耦合 耦合到第一晶体管125的第二电流电极和耦合到第一电源电压端子的第二端子。 在特定实施例中，非易失性存储单元包括耦合到所述可熔元件的第一端子的可熔元件编程电路140。 在另一特定实施例中，非易失性存储单元包括耦合到第一晶体管的控制电极的单元预置电路120。
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