公开(公告)号：US07286527B2

公开(公告)日：2007-10-23

申请号：US10205793

申请日：2002-07-26

申请人： Farid A. Yazdy ,  Kreg A. Martin

发明人： Farid A. Yazdy ,  Kreg A. Martin

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L49/357 ,  H04L43/0864 ,  H04L49/351 ,  H04L49/55

摘要： The link round trip delay between two switches in a Fibre Channel network may be determined by sending a particular timing signal value from an originating switch to a responding switch. The responding switch may store the timing signal value in an “echo” register for comparison to subsequently received timing signals. The originating switch may then send the pre-selected timing signal to the responding switch while simultaneously starting a timer. When the responding switch receives the timing signal, it may compare the value of the received signal to that stored in its echo register. If the value, is the same, the responding switch may retransmit—i.e., echo—the timing signal to the originating switch. When the originating switch receives the echoed timing signal, it may stop its timer and compute the link round trip delay time. The computed link round trip delay time between the originating switch and the responding switch may be advantageously used in fabric routing algorithms.

摘要翻译： 在光纤通道网络中的两个交换机之间的链路往返延迟可以通过从特定的定时信号值从起始交换机发送到响应交换机来确定。 响应开关可以将定时信号值存储在“回波”寄存器中用于与随后接收的定时信号进行比较。 然后，始发交换机可以在同时启动定时器的同时将预先选择的定时信号发送到响应开关。 当响应开关接收到定时信号时，它可将接收信号的值与其回波寄存器中存储的值进行比较。 如果该值相同，则响应开关可以重新发送 - 即将定时信号发回到始发交换机。 当始发交换机接收到回波定时信号时，可能会停止其定时器并计算链路往返延迟时间。 在起始交换机和响应交换机之间计算的链路往返延迟时间可以有利地用于结构路由算法中。

公开(公告)号：US5546547A

公开(公告)日：1996-08-13

申请号：US189138

申请日：1994-01-28

申请人： Michael J. Bowes ,  Farid A. Yazdy

发明人： Michael J. Bowes ,  Farid A. Yazdy

IPC分类号： G06F13/16 ,  G06F13/18 ,  G06F13/00

CPC分类号： G06F13/1605 ,  G06F13/1684

摘要： An arbitration scheme for a computer system in which a digital signal processor resides on the computer system's memory bus without requiring a block of dedicated static random access memory. An arbitration cycle is divided into 10 slices of which 5 slices are provided in each arbitration loop to the digital signal processor. Two slices are provided each to the system's I/O interface and to the peripheral bus controller. A final slice is provided to the system's CPU. A default state when no memory bus resource is requesting the system memory bus parks the memory bus on the CPU. The arbitration scheme provides sufficient bandwidth for real-time signal processing by the digital signal processor operating from the system's dynamic random access memory while also providing sufficient bandwidth for a local area network interface through the system's I/O interface.

摘要翻译： 一种用于计算机系统的仲裁方案，其中数字信号处理器驻留在计算机系统的存储器总线上，而不需要专用的静态随机存取存储器块。 仲裁周期分为10个片，每个仲裁循环中提供5个片到数字信号处理器。 每个系统的I / O接口和外设总线控制器都提供两个切片。 最后一个切片被提供给系统的CPU。 无内存总线资源请求系统内存总线时停止CPU上的内存总线的默认状态。 仲裁方案为通过系统的动态随机存取存储器操作的数字信号处理器提供足够的带宽用于实时信号处理，同时还通过系统的I / O接口为局域网接口提供足够的带宽。

公开(公告)号：US5708783A

公开(公告)日：1998-01-13

申请号：US430454

申请日：1995-04-28

申请人： Farid A. Yazdy

发明人： Farid A. Yazdy

IPC分类号： G06F13/362

CPC分类号： G06F13/362

摘要： A data bus arbiter for supporting pipelined transactions employs a circular FIFO for storing bus requests. The arbiter includes two pointers which reference the entries of the FIFO. A first pointer is incremented upon detection of the end of a bus cycle. A second pointer is incremented when a new bus cycle is started.

摘要翻译： 用于支持流水线交易的数据总线仲裁器采用循环FIFO来存储总线请求。 仲裁器包括引用FIFO条目的两个指针。 检测到总线周期的结束时，第一个指针递增。 当新的总线周期启动时，第二个指针递增。

公开(公告)号：US5600802A

公开(公告)日：1997-02-04

申请号：US212457

申请日：1994-03-14

申请人： Farid A. Yazdy ,  Michael J. Dhuey

发明人： Farid A. Yazdy ,  Michael J. Dhuey

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4063

摘要： Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches. When the computer is turned on, the BTU coupled to the data bus sequentially clears all valid bits in the tag cache, whereafter the cache and memory map are enabled. The 040 processor on the main board is disabled after power-up by using the 040 JTAG test port after inactivating the power-on fast reset. By shifting in appropriate RESET, TCK, and TMS patterns, the 040 will be placed in a nonfunctional, high impedance state. However, DRAM present on the motherboard may be accessed by the 601 after a cache miss. DRAM is accessed via a 601-040 transaction translation operation within the BTU, wherein coded tables map the MPC601 transaction into the appropriate 040 transaction.

摘要翻译： 公开了用于使用可选的外围附加卡升级基于040的个人计算机系统的电路布置和方法。 在一个实施例中，本发明包括基于PowerPC的微处理器，诸如MPC601，其具有布置为标签和数据块的一兆字节的车载直接映射级2外部高速缓冲存储器。 基于PowerPC的电路板插入与040微处理器共享数据和地址总线的处理器直接数据通路。 系统随机存取存储器（RAM），I / O和其他功能块存在于包含基于040的计算机的主板上。 MPC601通过地址和数据总线耦合到标签缓存，总线转换单元（BTU），存储用于PowerPC微处理器的操作系统代码的只读存储器（ROM），数据高速缓存，双频时钟缓冲器和 其他接口组件，例如包括地址和数据锁存器的处理器直接数据路径。 当计算机打开时，耦合到数据总线的BTU顺序地清除标签高速缓存中的所有有效位，之后启用高速缓存和存储器映射。 上电后，主板上的040处理器在禁用上电快速复位后使用040 JTAG测试端口禁用。 通过在适当的RESET，TCK和TMS模式下移位，040将处于非功能，高阻抗状态。 然而，存在于主板上的DRAM可能在高速缓存未命中之后由601访问。 通过BTU内的601-040事务翻译操作访问DRAM，其中编码表将MPC601事务映射到适当的040事务。

公开(公告)号：US5515514A

公开(公告)日：1996-05-07

申请号：US535761

申请日：1995-09-28

申请人： Michael J. Dhuey ,  Farid A. Yazdy

发明人： Michael J. Dhuey ,  Farid A. Yazdy

IPC分类号： G06F12/08 ,  G06F13/40 ,  G06F15/76

CPC分类号： G06F12/0866 ,  G06F13/4068

摘要： Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches. When the computer is turned on, the BTU coupled to the data bus sequentially clears all valid bits in the tag cache, whereafter the cache and memory map are enabled. The 040 processor on the main board is disabled after power-up by using the 040 JTAG test port after inactivating the power-on fast reset. By shifting in appropriate RESET, TCK, and TMS patterns, the 040 will be placed in a nonfunctional, high impedance state. However, DRAM present on the motherboard may be accessed by the 601 after a cache miss. DRAM is accessed via a 601-040 transaction translation operation within the BTU, wherein coded tables map the MPC601 transaction into the appropriate 040 transaction.

摘要翻译： 公开了用于使用可选的外围附加卡升级基于040的个人计算机系统的电路布置和方法。 在一个实施例中，本发明包括基于PowerPC的微处理器，诸如MPC601，其具有布置为标签和数据块的一兆字节的车载直接映射级2外部高速缓冲存储器。 基于PowerPC的电路板插入与040微处理器共享数据和地址总线的处理器直接数据通路。 系统随机存取存储器（RAM），I / O和其他功能块存在于包含基于040的计算机的主板上。 MPC601通过地址和数据总线耦合到标签缓存，总线转换单元（BTU），存储用于PowerPC微处理器的操作系统代码的只读存储器（ROM），数据高速缓存，双频时钟缓冲器和 其他接口组件，例如包括地址和数据锁存器的处理器直接数据路径。 当计算机打开时，耦合到数据总线的BTU顺序地清除标签高速缓存中的所有有效位，之后启用高速缓存和存储器映射。 上电后，主板上的040处理器在禁用上电快速复位后使用040 JTAG测试端口禁用。 通过在适当的RESET，TCK和TMS模式下移位，040将处于非功能，高阻抗状态。 然而，存在于主板上的DRAM可能在高速缓存未命中之后由601访问。 通过BTU内的601-040事务翻译操作访问DRAM，其中编码表将MPC601事务映射到适当的040事务。

公开(公告)号：US5812815A

公开(公告)日：1998-09-22

申请号：US430450

申请日：1995-04-28

申请人： Farid A. Yazdy

发明人： Farid A. Yazdy

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0831 ,  G06F12/0802

摘要： Systems and methods which provide a minimized address tenure to create more efficient memory transactions where the address is not needed for longer than the initial clock cycle in which it is used are described. The exceptions, for example, wherein the address is needed later during the transaction to perform a cache operation, are handled by reasserting the address using the cache controller. In this way, memory transactions are made more efficient but without the use of external latches conventionally used to preserve the deasserted address.

摘要翻译： 描述了提供最小化地址占有权以创建更有效的存储器事务的系统和方法，其中地址不需要长于其使用的初始时钟周期。 例如，其中在交易中稍后需要地址以执行高速缓存操作的例外是通过使用高速缓存控制器重新设置地址来处理的。 以这种方式，存储器事务变得更有效率，但是没有使用常规用于保留取消断言地址的外部锁存器。

公开(公告)号：US4887240A

公开(公告)日：1989-12-12

申请号：US132997

申请日：1987-12-15

申请人： Timothy L. Garverick ,  Farid A. Yazdy ,  Richard D. Henderson ,  Webster B. Meier

发明人： Timothy L. Garverick ,  Farid A. Yazdy ,  Richard D. Henderson ,  Webster B. Meier

IPC分类号： G11C11/406

CPC分类号： G11C11/406

摘要： According to the present invention, each successive refresh to the multiple banks of a DRAM array is staggered by one clock period. Thus, the time required to refresh one row in each DRAM of each bank at 10 MHz, for example, is equal to 0.7 .mu.sec., or 4.4% of the total allowable maximum time between refresh cycles. This staggered refresh technique avoids large power supply current spikes while minimizing the effect on memory access bandwidth.

公开(公告)号：US06256710B1

公开(公告)日：2001-07-03

申请号：US08430453

申请日：1995-04-28

申请人： Farid A. Yazdy ,  Michael Dhuey

发明人： Farid A. Yazdy ,  Michael Dhuey

IPC分类号： G06F1200

CPC分类号： G06F12/0888

摘要： Cache memory is managed to update the data stored in the cache regardless of whether the address being operated upon is designated as cache inhibited. In this way, the contents of the cache are coherent with main memory so that when the processor redesignates a noncacheable range of addresses to be cacheable, the cache does not need to be flushed. Read operations follow cache inhibit faithfully.

摘要翻译： 管理缓存存储器来更新存储在高速缓存中的数据，而不管被操作的地址是否被指定为缓存禁止。 以这种方式，缓存的内容与主存储器是一致的，使得当处理器重新指定不可缓存的地址范围以使其可高速缓存时，不需要刷新高速缓存。 读操作遵循缓存禁止忠实。

公开(公告)号：US5901295A

公开(公告)日：1999-05-04

申请号：US430451

申请日：1995-04-28

申请人： Farid A. Yazdy

发明人： Farid A. Yazdy

IPC分类号： G06F13/362

CPC分类号： G06F13/362

摘要： An arbiter employs both an address bus arbiter and a data bus arbiter for supporting pipelined, split bus transactions. The address arbiter may be implemented using a state machine. A first through third states of the state machine grant the address bus to a respective first through third bus masters, each having a different priority associated therewith. Idle states are interposed between states. The data bus arbiter may be implemented using a circular FIFO having a plurality of pointers to keep track of present and future bus masters using the data bus.

摘要翻译： 仲裁器采用地址总线仲裁器和数据总线仲裁器来支持流水线，分接总线事务。 地址仲裁器可以使用状态机来实现。 国家机器的第一到第三状态将地址总线授予相应的第一至第三总线主机，每个具有与其相关联的不同优先级。 空闲状态介于状态之间。 数据总线仲裁器可以使用具有多个指针的循环FIFO来实现，以使用数据总线来跟踪当前和将来的总线主控器。

公开(公告)号：US5815676A

公开(公告)日：1998-09-29

申请号：US859392

申请日：1997-05-20

申请人： Farid A. Yazdy

发明人： Farid A. Yazdy

IPC分类号： G06F13/362

CPC分类号： G06F13/362

摘要： An address bus arbiter is implemented using a state machine. A first through third states of the state machine grant the address bus to a respective first through third bus masters, each having a different priority associated therewith. Idle states are interposed between states. The idle state may be reached from one the bus grant states when a cache controller initiates a tag invalidation cycle or a cache allocation cycle. The idle state may also be reached when a first bus master commences a transaction cycle with a second bus master.

摘要翻译： 使用状态机实现地址总线仲裁器。 国家机器的第一到第三状态将地址总线授予相应的第一至第三总线主机，每个具有与其相关联的不同优先级。 空闲状态介于状态之间。 当高速缓存控制器启动标签无效循环或高速缓存分配周期时，可以从一个总线授权状态到达空闲状态。 当第一总线主机与第二总线主机开始事务循环时，也可以达到空闲状态。