公开(公告)号：US07202871B2

公开(公告)日：2007-04-10

申请号：US10843442

申请日：2004-05-12

申请人： Gavril Margittai ,  Zeev Sperber ,  Gabi Malka

发明人： Gavril Margittai ,  Zeev Sperber ,  Gabi Malka

IPC分类号： G06F13/18 ,  G06F15/80 ,  G06T1/20 ,  G06T11/40

CPC分类号： G06T15/04

摘要： An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.

摘要翻译： 用于平衡多管道纹理引擎中的并行纹理管道发出的存储器请求的仲裁机制。 该机制确保，由于纹理引擎处理多边形纹理，所有与给定图形纹理的一部分相关联的存储器请求将在任何纹理流水线发布对图形的另一部分的存储器请求之前由所有纹理管线发出 质地。 因此，本发明平衡了在一起操作的并行纹理管线之间的图形纹理处理，从而提高处理效率并防止死锁状况。

公开(公告)号：US06944720B2

公开(公告)日：2005-09-13

申请号：US10402827

申请日：2003-03-27

申请人： Zeev Sperber ,  Guy Peled ,  Doron Orenstein ,  Ehud Cohen ,  Gabi Malka

发明人： Zeev Sperber ,  Guy Peled ,  Doron Orenstein ,  Ehud Cohen ,  Gabi Malka

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0875 ,  G06F12/1054 ,  G06F2212/401

摘要： A memory system is provided for storing multiple data types. The memory system includes a main memory, a local cache, and a translation unit. The local cache has multiple entries, each of which includes a data field to store data and a status field to indicate a storage state for the stored data. The translation unit includes a translation lookaside buffer (TLB) and a status-cache (STC). The TLB stores address translations for data in the main memory, and the STC stores storage states for data indicated by the address translations.

摘要翻译： 提供了一种用于存储多种数据类型的存储器系统。 存储器系统包括主存储器，本地高速缓存和翻译单元。 本地缓存具有多个条目，每个条目包括用于存储数据的数据字段和用于指示所存储的数据的存储状态的状态字段。 翻译单元包括翻译后备缓冲器（TLB）和状态缓存（STC）。 TLB存储主存储器中的数据的地址转换，并且STC存储由地址转换指示的数据的存储状态。

公开(公告)号：US07076614B2

公开(公告)日：2006-07-11

申请号：US09896234

申请日：2001-06-29

申请人： Zeev Sperber ,  Gabi Malka ,  Gilad Shmueli ,  Shmulik Branski

发明人： Zeev Sperber ,  Gabi Malka ,  Gilad Shmueli ,  Shmulik Branski

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G09G5/39

摘要： A system and method of optimizing system memory bus bandwidth in a computer system. The system prepares to receive first data from system memory in accordance with at least one read request by evicting previously stored second data to a write back buffer. The at least one read request is then issued consecutively to system memory via the system memory bus. After issuance of the at least one read request, at least one write request is issued consecutively to send the second data in the write back buffer to the system memory via the system memory bus. The consecutive issuance of read and write requests avoids read-to-write and write-to-read bubbles that occur when alternating read and write requests are issued to system memory.

摘要翻译： 一种在计算机系统中优化系统内存总线带宽的系统和方法。 根据至少一个读取请求，系统准备从系统存储器接收第一数据，通过将先前存储的第二数据驱逐到回写缓冲器。 然后，至少一个读请求经由系统存储器总线连续地发送到系统存储器。 在发出至少一个读取请求之后，连续发出至少一个写入请求，以经由系统存储器总线将写入缓冲器中的第二数据发送到系统存储器。 读取和写入请求的连续发送避免了在将读写请求交给系统内存时发生的读写写入和写入读取的气泡。

公开(公告)号：US06557083B1

公开(公告)日：2003-04-29

申请号：US09608787

申请日：2000-06-30

申请人： Zeev Sperber ,  Guy Peled ,  Doron Orenstein ,  Ehud Cohen ,  Gabi Malka

发明人： Zeev Sperber ,  Guy Peled ,  Doron Orenstein ,  Ehud Cohen ,  Gabi Malka

IPC分类号： G06F1210

CPC分类号： G06F12/0875 ,  G06F12/1054 ,  G06F2212/401

摘要： A memory system is provided for storing multiple data types. The memory system includes a main memory, a local cache, and a translation unit. The local cache has multiple entries, each of which includes a data field to store data and a status field to indicate a storage state for the stored data. The translation unit includes a translation lookaside buffer (TLB) and a status-cache (STC). The TLB stores address translations for data in the main memory, and the STC stores storage states for data indicated by the address translations.

公开(公告)号：US20050264579A1

公开(公告)日：2005-12-01

申请号：US11191057

申请日：2005-07-28

申请人： Gabi Malka ,  Zeev Sperber ,  Yael Shenhav

发明人： Gabi Malka ,  Zeev Sperber ,  Yael Shenhav

IPC分类号： G06T11/40 ,  G06T15/00 ,  G06T15/04 ,  G09G5/00

CPC分类号： G06T15/005 ,  G06T15/04

摘要： A mechanism for synchronizing state variables used by texture pipelines in a multi-pipeline graphics texture engine. The mechanism ensures that, as polygons are processed by a texture engine, the state variables associated with each polygon are distributed in parallel to each texture pipeline, regardless of whether the texture engine is processing a single texture or a blend of different textures. When the texture engine processes a blend of different textures, signals controlling the operation of multiple texture pipelines are asserted. However, when the texture engine processes a single texture for a polygon, an embodiment of the invention continues to distribute received state variables to each of the texture pipelines, but only triggers the processing portion of the texture pipeline performing the single texture operation. The processing portions of the remaining texture pipelines may not be not triggered. Thus, the invention maintains the consistency of received polygon state variables across parallel texture pipelines while simultaneously providing for efficient use of a multi-pipeline texture engine by triggering only one texture pipeline when a single texture operation is required.

摘要翻译： 用于在多管道图形纹理引擎中同步由纹理管线使用的状态变量的机制。 该机制确保，随着多边形由纹理引擎处理，与每个多边形相关联的状态变量与每个纹理管线平行分布，而不管纹理引擎是处理单个纹理还是不同纹理的混合。 当纹理引擎处理不同纹理的混合时，控制多个纹理管线的操作的信号被断言。 然而，当纹理引擎处理多边形的单个纹理时，本发明的实施例继续将接收到的状态变量分配到每个纹理管线，而仅触发执行单个纹理操作的纹理流水线的处理部分。 剩余纹理流水线的处理部分可能不会被触发。 因此，本发明保持接收的多边形状态变量在并行纹理管线之间的一致性，同时通过仅在需要单个纹理操作时仅触发一个纹理流水线来提供多管线纹理引擎的有效使用。

公开(公告)号：US06580427B1

公开(公告)日：2003-06-17

申请号：US09608950

申请日：2000-06-30

申请人： Doron Orenstein ,  Guy Peled ,  Zeev Sperber ,  Ehud Cohen ,  Gabi Malka

发明人： Doron Orenstein ,  Guy Peled ,  Zeev Sperber ,  Ehud Cohen ,  Gabi Malka

IPC分类号： G06T1700

CPC分类号： G06T15/405

摘要： A graphics system is provided to implement compression of depth or z-data. The graphic system includes a buffer, a status table, and a read/write unit. The buffer stores depth data for multiple blocks of pixels in associated buffer entries. The status table stores status values for the entries of the buffer. The status value for a given entry indicates an access mode for the corresponding depth data according to whether the data is compressed, uncompressed or in a reference state. The read/write unit implements data accesses for a given entry responsive to the status value associated with the entry.

摘要翻译： 提供图形系统来实现深度或z数据的压缩。 图形系统包括缓冲器，状态表和读/写单元。 缓冲器存储相关缓冲区条目中多个像素块的深度数据。 状态表存储缓冲区条目的状态值。 根据数据是压缩的，未压缩的还是参考状态，给定条目的状态值表示对应的深度数据的访问模式。 读取/写入单元响应于与条目相关联的状态值来实现给定条目的数据访问。

公开(公告)号：US06947053B2

公开(公告)日：2005-09-20

申请号：US09963547

申请日：2001-09-27

申请人： Gabi Malka ,  Zeev Sperber ,  Yael Shenhav

发明人： Gabi Malka ,  Zeev Sperber ,  Yael Shenhav

IPC分类号： G06T11/40 ,  G06T15/00 ,  G06T15/04 ,  G09G5/00

CPC分类号： G06T15/005 ,  G06T15/04

摘要： A mechanism for synchronizing state variables used by texture pipelines in a multi-pipeline graphics texture engine. The mechanism ensures that, as polygons are processed by a texture engine, the state variables associated with each polygon are distributed in parallel to each texture pipeline, regardless of whether the texture engine is processing a single texture or a blend of different textures. When the texture engine processes a blend of different textures, signals controlling the operation of multiple texture pipelines are asserted. However, when the texture engine processes a single texture for a polygon, an embodiment of the invention continues to distribute received state variables to each of the texture pipelines, but only triggers the processing portion of the texture pipeline performing the single texture operation. The processing portions of the remaining texture pipelines may not be not triggered. Thus, the invention maintains the consistency of received polygon state variables across parallel texture pipelines while simultaneously providing for efficient use of a multi-pipeline texture engine by triggering only one texture pipeline when a single texture operation is required.

公开(公告)号：US06781588B2

公开(公告)日：2004-08-24

申请号：US09964802

申请日：2001-09-28

申请人： Gavril Margittai ,  Zeev Sperber ,  Gabi Malka

发明人： Gavril Margittai ,  Zeev Sperber ,  Gabi Malka

IPC分类号： G06F1318

CPC分类号： G06T15/04

摘要： An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.

公开(公告)号：US20150261270A1

公开(公告)日：2015-09-17

申请号：US14207074

申请日：2014-03-12

申请人： OMER VIKINSKI ,  IGOR YANOVER ,  GAVRI BERGER ,  GABI MALKA ,  ZEEV SPERBER

发明人： OMER VIKINSKI ,  IGOR YANOVER ,  GAVRI BERGER ,  GABI MALKA ,  ZEEV SPERBER

IPC分类号： G06F1/26 ,  G06F9/50

CPC分类号： G06F1/26 ,  G06F1/28 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/24

摘要： A processor and method are described for performing proactive throttling of execution unit ports. For example, one embodiment of a processor core comprises: a plurality of execution unit ports within an execution stage of the processor core; a scheduler unit to schedule execution of a plurality of operations to the plurality of execution unit ports; and proactive throttling logic to limit acceleration of execution of the operations by the ports to an acceleration level which does not result in significant power supply droops.

摘要翻译： 描述了用于执行执行单元端口的主动式节流的处理器和方法。 例如，处理器核心的一个实施例包括：处理器核心的执行阶段内的多个执行单元端口; 调度单元，对多个执行单元端口进行多个操作的执行; 以及主动节流逻辑，以将端口的操作的执行加速度限制到不会导致显着的电源下降的加速度水平。

公开(公告)号：US20140189314A1

公开(公告)日：2014-07-03

申请号：US13730834

申请日：2012-12-29

申请人： Tsvika Kurts ,  Ofer Levy ,  Itamar Kazachinsky ,  Gabi Malka ,  Zeev Sperber ,  Jason W. Brandt

发明人： Tsvika Kurts ,  Ofer Levy ,  Itamar Kazachinsky ,  Gabi Malka ,  Zeev Sperber ,  Jason W. Brandt

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F11/00 ,  G06F11/3471 ,  G06F11/36 ,  G06F13/4068 ,  G06F2201/865

摘要： A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

摘要翻译： 一方面的方法包括为处理器的第一逻辑处理器生成实时指令跟踪（RTIT）分组。 RTIT分组指示由第一逻辑处理器执行的软件的流程。 RTIT分组被存储在对应于第一逻辑处理器的RTIT队列中。 RTIT数据包主要通过处理器的固件从RTIT队列传送到存储器。 还公开了其它方法，装置和系统。