Storage device and method for using a virtual file in a public memory area to access a plurality of protected files in a private memory area
    1.
    发明授权
    Storage device and method for using a virtual file in a public memory area to access a plurality of protected files in a private memory area 有权
    用于在公共存储器区域中使用虚拟文件来访问私人存储器区域中的多个受保护文件的存储装置和方法

    公开(公告)号:US09092597B2

    公开(公告)日:2015-07-28

    申请号:US12634470

    申请日:2009-12-09

    摘要: A storage device and method for using a virtual file in a public memory area to access a plurality of protected files in a private memory area are disclosed. In one embodiment, a storage device receives a request from a host for access to a virtual file in the public memory area, wherein the virtual file is associated with a plurality of protected files stored in the private memory area. The storage device responds to the request by selecting and providing the host with access to one of the plurality of protected files stored in the private memory area. The storage device receives an additional request from the host for access to the virtual file and responds to the additional request by selecting and providing the host with access to a different one of the plurality of protected files stored in the private memory area.

    摘要翻译: 公开了一种用于在公共存储区域中使用虚拟文件来访问专用存储器区域中的多个受保护文件的存储装置和方法。 在一个实施例中,存储设备从主机接收对公共存储器区域中的虚拟文件的访问的请求,其中虚拟文件与存储在专用存储器区域中的多个受保护文件相关联。 存储设备通过选择并提供主机对存储在专用存储器区域中的多个受保护文件之一的访问来响应该请求。 存储设备从主机接收对虚拟文件的访问的附加请求,并且通过选择并向主机提供对存储在专用存储器区域中的多个受保护文件中的不同的一个的访问来响应附加请求。

    Efficient dynamic stimulation in an implanted device
    4.
    发明授权
    Efficient dynamic stimulation in an implanted device 失效
    在植入装置中有效的动态刺激

    公开(公告)号:US08423132B2

    公开(公告)日:2013-04-16

    申请号:US10538521

    申请日:2003-12-11

    IPC分类号: A61N1/00

    摘要: A method for measuring impedance of a tissue (20), consisting of charging a capacitor (C15) to a potential, and discharging the capacitor for a discharge period through the tissue. The method further consists of measuring a voltage drop on the capacitor over the discharge period and determining the impedance of the tissue responsive to the potential, the voltage drop, and the discharge period.

    摘要翻译: 一种用于测量组织(20)的阻抗的方法,包括将电容器(C15)充电到电位,并且通过所述组织将电容器放电放电期间。 该方法还包括在放电周期内测量电容器上的电压降,并根据电位,电压降和放电周期确定组织的阻抗。

    Electrode assembly for nerve control
    9.
    发明授权
    Electrode assembly for nerve control 有权
    用于神经控制的电极组件

    公开(公告)号:US08116881B2

    公开(公告)日:2012-02-14

    申请号:US11978776

    申请日:2007-10-29

    IPC分类号: A61N1/05

    摘要: Apparatus is provided for applying current to a nerve, including a housing, configured to be placed in a vicinity of the nerve. At least one electrode is fixed to the housing such that the at least one electrode does not come in direct physical contact with the nerve when the housing is placed in the vicinity of the nerve, and such that the electrode surrounds greater than 180 degrees of a circumference of the nerve after the placement of the housing. Two end insulating elements are fixed to the housing such that the at least one electrode is between the end insulating elements, and the end insulating elements come in contact or practically in contact with the nerve when the housing is placed in the vicinity of the nerve. Other embodiments are also described.

    摘要翻译: 提供了用于将电流施加到神经的装置,包括被配置为放置在神经附近的壳体。 至少一个电极被固定到壳体,使得当壳体放置在神经附近时,至少一个电极不会与神经直接物理接触,并且使得电极围绕大于180度的 放置外壳后神经的周长。 两个端部绝缘元件固定到壳体上,使得至少一个电极位于端部绝缘元件之间,并且当壳体放置在神经附近时,端部绝缘元件接触或实际上与神经接触。 还描述了其它实施例。

    METHOD AND SYSTEM TO REDUCE THE POWER CONSUMPTION OF A MEMORY DEVICE
    10.
    发明申请
    METHOD AND SYSTEM TO REDUCE THE POWER CONSUMPTION OF A MEMORY DEVICE 有权
    降低存储器件功耗的方法和系统

    公开(公告)号:US20110320723A1

    公开(公告)日:2011-12-29

    申请号:US12823047

    申请日:2010-06-24

    IPC分类号: G06F12/08

    摘要: A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is logic coupled with the data cache memory to facilitate access to only part of the N-ways of the N-way set-associative L1 cache memory in response to a load instruction or a store instruction. By reducing the number of ways to access the N-way set-associative L1 cache memory for each load or store request, the power requirements of the N-way set-associative L1 cache memory is reduced in one embodiment of the invention. In one embodiment of the invention, when a prediction is made that the accesses to cache memory only requires the data arrays of the N-way set-associative L1 cache memory, the access to the fill buffers are deactivated or disabled.

    摘要翻译: 一种降低存储器件功耗的方法和系统。 在本发明的一个实施例中,存储器件是N路组合关联级(L1)高速缓冲存储器,并且存在与数据高速缓冲存储器耦合的逻辑,以便于仅访问N- 响应于加载指令或存储指令,单向设置关联L1高速缓冲存储器。 通过减少针对每个加载或存储请求访问N路组合关联的L1高速缓冲存储器的方法的数量,在本发明的一个实施例中,减少了N路组合关联的L1高速缓冲存储器的功率需求。 在本发明的一个实施例中,当预测到对高速缓存存储器的访问仅需要N路组关联的L1高速缓冲存储器的数据阵列时,对填充缓冲器的访问被去激活或禁用。