公开(公告)号：US07400183B1

公开(公告)日：2008-07-15

申请号：US11415588

申请日：2006-05-01

申请人： Mohandas Palatholmana Sivadasan ,  Gajendar Rohilla

发明人： Mohandas Palatholmana Sivadasan ,  Gajendar Rohilla

IPC分类号： H03H11/26

CPC分类号： H03H11/265 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L7/0995

摘要： A delay cell circuit (200) is disclosed. The delay cell circuit may include a differential stage (202) and a cross-coupled stage (204). The cross-coupled stage can include resistors (210-0 and 210-1) the function to reduce a gain. The differential stage (202) and cross-coupled stage (204) can include variable currents sources (208 and 212), respectively. As frequency of operation increases, variable current source (208) provides a larger current to the differential stage (202) and variable current source (212) provides a smaller current to cross-coupled stage (204). Delay cell circuit (200) may be used in a voltage controlled oscillator (VCO). By including gain attenuating devices such as resistors (210-0 and 210-1), a frequency tuning range of the VCO may be increased.

摘要翻译： 公开了一种延迟单元电路（200）。 延迟单元电路可以包括差分级（202）和交叉耦合级（204）。 交叉耦合级可以包括用于减小增益的功能的电阻器（210-0和210-1）。 差分级（202）和交叉耦合级（204）可分别包括可变电流源（208和212）。 随着操作频率的增加，可变电流源（208）向差分级（202）提供更大的电流，并且可变电流源（212）向交叉耦合级（204）提供较小的电流。 延迟单元电路（200）可以用在压控振荡器（VCO）中。 通过包括诸如电阻器（210-0和210-1）的增益衰减器件，可以增加VCO的频率调谐范围。

公开(公告)号：US08174291B1

公开(公告)日：2012-05-08

申请号：US10875888

申请日：2004-06-24

申请人： Pulkit Shah ,  Gajendar Rohilla

发明人： Pulkit Shah ,  Gajendar Rohilla

IPC分类号： H03K5/22

CPC分类号： H03K5/1565

摘要： An improved buffer circuit and method for minimizing (or altogether eliminating) duty cycle distortion between input and output signals of the buffer circuit are provided herein. In general, the improved buffer circuit essentially decouples the charging and discharging current paths of the buffer circuit from a reference voltage supplied to the buffer circuit. This ensures substantially equal time delays between rising and falling edges of the input and output signals, thereby decreasing duty cycle distortion and maintaining a maximum operating frequency of the buffer circuit, even when the reference voltage approaches a transistor threshold voltage. In addition, the improved method may include forwarding an input signal with an input duty cycle onto mutually connected gate terminals of a pair of pull-down transistors, and activating/inactivating at least one of the pair of pull-down transistors during logic high and logic low voltage values of the input duty cycle, respectively. In this manner, the method provides an output signal with an output duty cycle that is substantially equal to the input duty cycle.

摘要翻译： 本文提供了一种用于在缓冲电路的输入和输出信号之间最小化（或完全消除）占空比失真的改进的缓冲电路和方法。 通常，改进的缓冲电路基本上将缓冲电路的充电和放电电流路径与提供给缓冲电路的参考电压相分离。 这确保输入和输出信号的上升沿和下降沿之间的时间延迟基本上相等，从而即使当参考电压接近晶体管阈值电压时，减小占空比失真并保持缓冲电路的最大工作频率。 此外，改进的方法可以包括将具有输入占空比的输入信号转发到一对下拉晶体管的相互连接的栅极端子上，以及在逻辑高电平期间激活/去激活一对下拉晶体管中的至少一个，以及 输入占空比的逻辑低电压值。 以这种方式，该方法提供具有基本上等于输入占空比的输出占空比的输出信号。

公开(公告)号：US08120408B1

公开(公告)日：2012-02-21

申请号：US12218404

申请日：2008-07-14

申请人： Mohandas Palatholmana Sivadasan ,  Gajendar Rohilla

发明人： Mohandas Palatholmana Sivadasan ,  Gajendar Rohilla

IPC分类号： H03H11/26

CPC分类号： H03H11/265 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L7/0995

摘要： A delay cell circuit (200) is disclosed. The delay cell circuit may include a differential stage (202) and a cross-coupled stage (204). The cross-coupled stage can include resistors (210-0 and 210-1) the function to reduce a gain. The differential stage (202) and cross-coupled stage (204) can include variable currents sources (208 and 212), respectively. As frequency of operation increases, variable current source (208) provides a larger current to the differential stage (202) and variable current source (212) provides a smaller current to cross-coupled stage (204). Delay cell circuit (200) may be used in a voltage controlled oscillator (VCO). By including gain attenuating devices such as resistors (210-0 and 210-1), a frequency tuning range of the VCO may be increased.

摘要翻译： 公开了一种延迟单元电路（200）。 延迟单元电路可以包括差分级（202）和交叉耦合级（204）。 交叉耦合级可以包括用于减小增益的功能的电阻（210-0和210-1）。 差分级（202）和交叉耦合级（204）可分别包括可变电流源（208和212）。 随着操作频率的增加，可变电流源（208）向差分级（202）提供更大的电流，并且可变电流源（212）向交叉耦合级（204）提供较小的电流。 延迟单元电路（200）可以用在压控振荡器（VCO）中。 通过包括诸如电阻（210-0和210-1）的增益衰减器件，可以增加VCO的频率调谐范围。