公开(公告)号：US09294211B2

公开(公告)日：2016-03-22

申请号：US14008553

申请日：2011-07-07

申请人： Srinivas Rao ,  Gajendra Singh Ranka

发明人： Srinivas Rao ,  Gajendra Singh Ranka

IPC分类号： H04J3/02 ,  H04J3/04 ,  H04J3/14 ,  H04J3/06

CPC分类号： H04J3/02 ,  H04J3/04 ,  H04J3/0691 ,  H04J3/14 ,  H04J2203/0057 ,  H04J2203/0089

摘要： Embodiments of the disclosure relate to a method and system for enhancing management channels. The method comprises operating TDM (Time Division Multiplex) clock frequency at a predefined rate higher than operating frequency based on available management channels. Transmitting data on the management channels using the TDM slots of a TDM based controller at a higher frequency rate.

摘要翻译： 本公开的实施例涉及用于增强管理信道的方法和系统。 该方法包括基于可用管理信道以比工作频率高的预定速率操作TDM（时分多路复用）时钟频率。 使用基于TDM的控制器的TDM时隙以更高的频率速率在管理信道上发送数据。

公开(公告)号：US20140064302A1

公开(公告)日：2014-03-06

申请号：US14008553

申请日：2011-07-07

申请人： Srinivas Rao ,  Gajendra Singh Ranka

发明人： Srinivas Rao ,  Gajendra Singh Ranka

IPC分类号： H04J3/02

CPC分类号： H04J3/02 ,  H04J3/04 ,  H04J3/0691 ,  H04J3/14 ,  H04J2203/0057 ,  H04J2203/0089

摘要： Embodiments of the disclosure relate to a method and system for enhancing management channels. The method comprises operating TDM (Time Division Multiplex) clock frequency at a predefined rate higher than operating frequency based on available management channels. Transmitting data on the management channels using the TDM slots of a TDM based controller at a higher frequency rate.

摘要翻译： 本公开的实施例涉及用于增强管理信道的方法和系统。 该方法包括基于可用管理信道以比工作频率高的预定速率操作TDM（时分多路复用）时钟频率。 使用基于TDM的控制器的TDM时隙以更高的频率发送管理信道上的数据。

公开(公告)号：US20140044119A1

公开(公告)日：2014-02-13

申请号：US14008555

申请日：2011-07-08

申请人： Srinivas Rao ,  Gajendra Singh Ranka

发明人： Srinivas Rao ,  Gajendra Singh Ranka

IPC分类号： H04W56/00

CPC分类号： H04W56/0015 ,  H03K5/15

摘要： Embodiments of the present disclosure relate to a method and system for multiplexing the low frequency signals from at least one clock transmitter to at least one clock receiver to reduce interface count. The low frequency signals are multiplexed in a CLKMUX logic using selection signals. The selection signals are generated using system frame and system clocks. The multiplexed clock is received by the CLKDEMUX logic through an interface. The interface can be backplane connectors, PCB traces and cables. The CLKDEMUX logic dc-multiplexes the received clock and transmits to the SELECT LOGIC for selecting at least one low frequency clock. The SELECT LOGIC selects at least one low frequency clock based on the signals from a processor. The jitter attenuator filters jitter in the low frequency clock and the CLOCK SINK distributes system clocks to rest of system elements.

摘要翻译： 本公开的实施例涉及用于将来自至少一个时钟发射机的低频信号复用到至少一个时钟接收机以减少接口数量的方法和系统。 低频信号使用选择信号在CLKMUX逻辑中复用。 使用系统帧和系统时钟生成选择信号。 复用的时钟由CLKDEMUX逻辑通过接口接收。 该接口可以是背板连接器，PCB走线和电缆。 CLKDEMUX逻辑对所接收的时钟进行直流多路复用，并传输到SELECT LOGIC，以选择至少一个低频时钟。 SELECT LOGIC根据处理器的信号选择至少一个低频时钟。 抖动衰减器对低频时钟中的抖动进行滤波，CLOCK SINK将系统时钟分配给系统元件的其余部分。

公开(公告)号：US20140022887A1

公开(公告)日：2014-01-23

申请号：US14008552

申请日：2011-07-07

申请人： Srinivas Rao ,  Gajendra Singh Ranka

发明人： Srinivas Rao ,  Gajendra Singh Ranka

IPC分类号： H04J3/06

CPC分类号： H04J3/0638 ,  G06F11/2028 ,  G06F11/2033 ,  G06F11/2038 ,  H04J3/0641

摘要： Embodiments of the present disclosure relate to a Zero traffic hit synchronization switch over technique in a telecommunication network. The switch over is carried out by switching input reference of the receiver from one or more master (1) to at least one slave (2), wherein said slave (2) becomes new master (2) and said one or more master (1) becomes new slave (1) after switching. Now, the new master (2) locks to the new slave (1) for predetermined time period. Once the predetermined is elapsed, the new master (2) is disconnected from the new slave (1), wherein said new master (2) selects its own network reference clock upon disconnection of the new slave (1). The new slave (1) is locked to the new master (2) to synchronize the switchover in redundant systems.

摘要翻译： 本公开的实施例涉及电信网络中的零业务命中同步切换技术。 通过将接收机的输入参考从一个或多个主机（1）切换到至少一个从机（2）来进行切换，其中所述从机（2）变为新主机（2），并且所述一个或多个主机 ）在切换后成为新的从机（1）。 现在，新的主机（2）在预定的时间内锁定到新的从机（1）。 一旦经过预定，新的主机（2）与新的从机（1）断开连接，其中所述新的主机（2）在断开新的从机（1）时选择自己的网络参考时钟。 新的从站（1）被锁定到新的主站（2），以在冗余系统中同步切换。

公开(公告)号：US09537591B2

公开(公告)日：2017-01-03

申请号：US14008552

申请日：2011-07-07

申请人： Srinivas Rao ,  Gajendra Singh Ranka

发明人： Srinivas Rao ,  Gajendra Singh Ranka

IPC分类号： H04J3/06 ,  G06F11/20

CPC分类号： H04J3/0638 ,  G06F11/2028 ,  G06F11/2033 ,  G06F11/2038 ,  H04J3/0641

摘要： Embodiments of the present disclosure relate to a Zero traffic hit synchronization switch over technique in a telecommunication network. The switch over is carried out by switching input reference of the receiver from one or more master (1) to at least one slave (2), wherein said slave (2) becomes new master (2) and said one or more master (1) becomes new slave (1) after switching. Now, the new master (2) locks to the new slave (1) for predetermined time period. Once the predetermined is elapsed, the new master (2) is disconnected from the new slave (1), wherein said new master (2) selects its own network reference clock upon disconnection of the new slave (1). The new slave (1) is locked to the new master (2) to synchronize the switchover in redundant systems.

摘要翻译： 本公开的实施例涉及电信网络中的零业务命中同步切换技术。 通过将接收机的输入参考从一个或多个主机（1）切换到至少一个从机（2）来执行切换，其中所述从机（2）变为新主机（2），并且所述一个或多个主机 ）在切换后成为新的从机（1）。 现在，新的主机（2）在预定的时间内锁定到新的从机（1）。 一旦经过预定，新的主机（2）与新的从机（1）断开连接，其中所述新的主机（2）在断开新的从机（1）时选择自己的网络参考时钟。 新的从站（1）被锁定到新的主站（2），以在冗余系统中同步切换。

公开(公告)号：US09686762B2

公开(公告)日：2017-06-20

申请号：US14008555

申请日：2011-07-08

申请人： Srinivas Rao ,  Gajendra Singh Ranka

发明人： Srinivas Rao ,  Gajendra Singh Ranka

IPC分类号： H04W56/00 ,  H03K5/15

CPC分类号： H04W56/0015 ,  H03K5/15

摘要： Embodiments of the present disclosure relate to a method and system for multiplexing the low frequency signals from at least one clock transmitter to at least one clock receiver to reduce interface count. The low frequency signals are multiplexed in a CLKMUX logic using selection signals. The selection signals are generated using system frame and system clocks. The multiplexed clock is received by the CLKDEMUX logic through an interface. The interface can be backplane connectors, PCB traces and cables. The CLKDEMUX logic de-multiplexes the received clock and transmits to the SELECT LOGIC for selecting at least one low frequency clock. The SELECT LOGIC selects at least one low frequency clock based on the signals from a processor. The jitter attenuator filters jitter in the low frequency clock and the CLOCK SINK distributes system clocks to rest of system elements.

公开(公告)号：US09413696B2

公开(公告)日：2016-08-09

申请号：US14008554

申请日：2011-07-08

申请人： Srinivas Rao ,  Gajendra Singh Ranka

发明人： Srinivas Rao ,  Gajendra Singh Ranka

IPC分类号： H04L12/931 ,  G06F13/40 ,  G06F13/36

CPC分类号： H04L49/405 ,  G06F13/36 ,  G06F13/4068

摘要： The present disclosure discloses a system architecture and method for reducing pin count on a backplane connecting plurality of devices. In an embodiment, the signals from the plurality of devices are multiplexed or mapped into time slots using a MapMux device. The MapMux device then sends the multiplexed or mapped signals over backplane on TDM bus. The MapMux device at the receiving end de-multiplexes or de-maps and sends the received signals to plurality of devices for further processing. The present disclosure allows a large number of signals to be passed between the devices through a single stream.

摘要翻译： 本公开公开了一种用于减少连接多个设备的背板上的引脚数的系统架构和方法。 在一个实施例中，使用MapMux设备将来自多个设备的信号复用或映射到时隙中。 MapMux设备然后通过TDM总线上的背板发送多路复用或映射的信号。 接收端的MapMux设备解复用或解映射，并将接收到的信号发送到多个设备进行进一步处理。 本公开允许通过单个流在设备之间传递大量信号。

公开(公告)号：US20140086261A1

公开(公告)日：2014-03-27

申请号：US14008554

申请日：2011-07-08

申请人： Srinivas Rao ,  Gajendra Singh Ranka

发明人： Srinivas Rao ,  Gajendra Singh Ranka

IPC分类号： H04L12/931 ,  G06F13/36

CPC分类号： H04L49/405 ,  G06F13/36 ,  G06F13/4068

摘要： The present disclosure discloses a system architecture and method for reducing pin count on a backplane connecting plurality of devices. In an embodiment, the signals from the plurality of devices are multiplexed or mapped into time slots using a MapMux device. The MapMux device then sends the multiplexed or mapped signals over backplane on TDM bus. The MapMux device at the receiving end de-multiplexes or de-maps and sends the received signals to plurality of devices for further processing. The present disclosure allows a large number of signals to be passed between the devices through a single stream.

摘要翻译： 本公开公开了一种用于减少连接多个设备的背板上的引脚数的系统架构和方法。 在一个实施例中，使用MapMux设备将来自多个设备的信号复用或映射到时隙中。 MapMux设备然后通过TDM总线上的背板发送多路复用或映射的信号。 接收端的MapMux设备解复用或解映射，并将接收到的信号发送到多个设备进行进一步处理。 本公开允许通过单个流在设备之间传递大量信号。

公开(公告)号：US20140035635A1

公开(公告)日：2014-02-06

申请号：US13261745

申请日：2011-08-11

申请人： Srinivas Rao ,  Gajendra Singh Ranka

发明人： Srinivas Rao ,  Gajendra Singh Ranka

IPC分类号： H03L7/00

摘要： The invention relates to an apparatus and a method for glitch-free clock switching. In one embodiment this is accomplished by a first clock source, one or more second clock source and a clock switching control device configured to synchronize the receive input clock from the first clock source and the second clock source, and output at least one of the them according to control signal selection.

摘要翻译： 本发明涉及无毛刺时钟切换的装置和方法。 在一个实施例中，这通过第一时钟源，一个或多个第二时钟源和时钟切换控制装置来实现，时钟切换控制装置被配置为使来自第一时钟源和第二时钟源的接收输入时钟同步，并且输出它们中的至少一个 根据控制信号选择。