公开(公告)号：US20080029841A1

公开(公告)日：2008-02-07

申请号：US11869958

申请日：2007-10-10

申请人： George Feng ,  Louis Hsu ,  Rajiv Joshi

发明人： George Feng ,  Louis Hsu ,  Rajiv Joshi

IPC分类号： H01L29/00

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

摘要翻译： 一种通过在半导体衬底上形成虚设结构而在电子器件上选择性地形成电介质室的方法（和结构），在虚拟结构上沉积介电层，通过介电层形成通向虚拟结构的开口， 虚拟结构形成电介质室。

公开(公告)号：US20050199977A1

公开(公告)日：2005-09-15

申请号：US11129325

申请日：2005-05-16

申请人： George Feng ,  Louis Hsu ,  Rajiv Joshi

发明人： George Feng ,  Louis Hsu ,  Rajiv Joshi

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/00

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

公开(公告)号：US20050095837A1

公开(公告)日：2005-05-05

申请号：US10698483

申请日：2003-11-03

申请人： George Feng ,  Louis Hsu ,  Rajiv Joshi

发明人： George Feng ,  Louis Hsu ,  Rajiv Joshi

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/00

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

摘要翻译： 一种通过在半导体衬底上形成虚设结构而在电子器件上选择性地形成电介质室的方法（和结构），在虚拟结构上沉积介电层，通过介电层形成通向虚拟结构的开口， 虚拟结构形成电介质室。

公开(公告)号：US20050085096A1

公开(公告)日：2005-04-21

申请号：US10689233

申请日：2003-10-20

申请人： Kia Low ,  Larry Nesbit ,  George Feng

发明人： Kia Low ,  Larry Nesbit ,  George Feng

IPC分类号： H01L21/469 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L27/10864 ,  H01L27/10885

摘要： Low-k dielectric materials are incorporated as an insulator material between bit lines and an inter-level dielectric material. The device is first processed in a known manner, up to and including the deposition and anneal of the bit line metal, using a higher dielectric constant material that can withstand the higher temperature process steps as the insulator between the bit lines. Then, the higher dielectric constant material is removed using an etch that is selective to the bit line metal, and the low-k dielectric material is deposited. The low-k material may then be planarized to the top of the bit lines, and further low-k material deposited as an inter-level dielectric. Alternatively, sufficient low-k material is deposited in a single step to both fill the gaps between the bit lines as well as serve as an inter-level dielectric, and then the low-k dielectric material is planarized. Standard processing may then be carried out.

摘要翻译： 低k电介质材料作为位线和层间电介质材料之间的绝缘体材料并入。 首先使用能够承受作为位线之间的绝缘体的较高温度工艺步骤的较高介电常数材料，以已知的方式处理器件，直到并包括位线金属的沉积和退火。 然后，使用对位线金属有选择性的蚀刻去除较高的介电常数材料，并沉积低介电常数材料。 然后可以将低k材料平面化到位线的顶部，并且将另外的低k材料沉积为层间电介质。 或者，在单个步骤中沉积足够的低k材料，以填充位线之间的间隙以及用作层间电介质，然后将低k电介质材料平坦化。 然后可以执行标准处理。