公开(公告)号：US20050199977A1

公开(公告)日：2005-09-15

申请号：US11129325

申请日：2005-05-16

申请人： George Feng ,  Louis Hsu ,  Rajiv Joshi

发明人： George Feng ,  Louis Hsu ,  Rajiv Joshi

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/00

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

公开(公告)号：US20050095837A1

公开(公告)日：2005-05-05

申请号：US10698483

申请日：2003-11-03

申请人： George Feng ,  Louis Hsu ,  Rajiv Joshi

发明人： George Feng ,  Louis Hsu ,  Rajiv Joshi

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L29/00

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

摘要翻译： 一种通过在半导体衬底上形成虚设结构而在电子器件上选择性地形成电介质室的方法（和结构），在虚拟结构上沉积介电层，通过介电层形成通向虚拟结构的开口， 虚拟结构形成电介质室。

公开(公告)号：US20080029841A1

公开(公告)日：2008-02-07

申请号：US11869958

申请日：2007-10-10

申请人： George Feng ,  Louis Hsu ,  Rajiv Joshi

发明人： George Feng ,  Louis Hsu ,  Rajiv Joshi

IPC分类号： H01L29/00

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

摘要翻译： 一种通过在半导体衬底上形成虚设结构而在电子器件上选择性地形成电介质室的方法（和结构），在虚拟结构上沉积介电层，通过介电层形成通向虚拟结构的开口， 虚拟结构形成电介质室。

公开(公告)号：US20070224801A1

公开(公告)日：2007-09-27

申请号：US11390390

申请日：2006-03-27

申请人： Chih-Chao Yang ,  Louis Hsu ,  Rajiv Joshi

发明人： Chih-Chao Yang ,  Louis Hsu ,  Rajiv Joshi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846

摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.

摘要翻译： 提供介电互连结构及其形成方法。 具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上 表面。 在典型的实施例中，通过用气体离子等离子体（例如，Ar，He，Ne，Xe，N 2，H 2，NH 3和N 2 H 2）。 在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。 此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

公开(公告)号：US20050275977A1

公开(公告)日：2005-12-15

申请号：US10867094

申请日：2004-06-14

申请人： Rajiv Joshi ,  Louis Hsu

发明人： Rajiv Joshi ,  Louis Hsu

IPC分类号： G06F1/26 ,  G11C5/14 ,  G11C11/4074 ,  H02H7/00

CPC分类号： G11C11/4074 ,  G06F1/26 ,  G11C5/14 ,  Y10T307/305

摘要： There is provided a method for managing a multi-level power supply. The method includes comparing a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and routing current from the lower voltage supply bus to the higher voltage supply bus if Vs2

摘要翻译： 提供了一种用于管理多电平电源的方法。 该方法包括将较低电压电源总线的电压电平（Vs 1）与较高电压电源总线的电压电平（Vs 2）进行比较，以及如果Vs 2将电流从低电压电源总线路由到较高电压电源总线

公开(公告)号：US20070184581A1

公开(公告)日：2007-08-09

申请号：US11347332

申请日：2006-02-03

申请人： Louis Hsu ,  Rajiv Joshi ,  Jack Mandelman

发明人： Louis Hsu ,  Rajiv Joshi ,  Jack Mandelman

IPC分类号： H01L21/00

CPC分类号： H01L23/3677 ,  H01L2924/0002 ,  H01L2924/10158 ,  Y10S438/928 ,  Y10S438/96 ,  Y10S438/977 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device includes etching a substrate to form a recess, the substrate being formed on a backside of a semiconductor wafer, forming pores in the substrate in an area of the recess, and forming in the recess a material having a thermal conductivity which is greater than a thermal conductivity of the substrate. In another aspect, a method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.

摘要翻译： 一种制造半导体器件的方法包括蚀刻衬底以形成凹部，所述衬底形成在半导体晶片的背面上，在所述凹部的区域中在所述衬底中形成孔，并且在所述凹部中形成具有热 电导率大于衬底的热导率。 另一方面，制造半导体器件的方法包括蚀刻形成在半导体晶片的背面上的衬底，以在衬底中形成凹陷，并且在凹部中形成溅射膜，溅射膜包括具有系数的第一材料 的热膨胀（CTE），其至少基本上等于衬底的CTE，以及具有大于衬底的热导率的导热性的第二材料。

公开(公告)号：US20050260801A1

公开(公告)日：2005-11-24

申请号：US10996866

申请日：2004-11-24

申请人： Rama Divakaruni ,  Louis Hsu ,  Rajiv Joshi ,  Carl Radens

发明人： Rama Divakaruni ,  Louis Hsu ,  Rajiv Joshi ,  Carl Radens

IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L29/66553 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78684

摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 FET包括在绝缘体层上的每个端部（例如，在绝缘体上的超薄绝缘体（SOI））芯片上的源极/漏极（RSD）区域上升的薄沟道。 在FET的每个端部，即在RSD区域的末端处的隔离沟槽隔离并限定FET岛。 每个RSD区域的绝缘侧壁将RSD区域之间的FET栅极夹在中间。 栅极电介质可以是高K电介质。 RSD区域上和可选地在栅极上的杀菌剂降低了器件电阻。

公开(公告)号：US20080049378A1

公开(公告)日：2008-02-28

申请号：US11927774

申请日：2007-10-30

申请人： Louis Hsu ,  Rajiv Joshi ,  Chun-Yung Sung

发明人： Louis Hsu ,  Rajiv Joshi ,  Chun-Yung Sung

IPC分类号： H01G4/20

CPC分类号： H01G4/228 ,  H01G4/33 ,  H01L21/768 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insulating layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insulating layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.

摘要翻译： 一种金属绝缘体金属（MIM）电容器，包括金属层，形成在金属层上的绝缘层，至少第一开口和形成在第一绝缘层中的至少第二开口，形成在第一开口中的电介质层 沉积在第一和第二开口中的导电材料和形成在第一开口上的第一金属板和形成在第二开口上的第二金属板。 一种制造MIM电容器的方法，包括形成第一金属层，在第一金属层上形成绝缘层，至少形成第一开口和至少第一绝缘层中的第二开口，在第二开口上沉积掩模 在第一开口中形成电介质层，去除掩模，在第一和第二开口中沉积导电材料，并在第一和第二开口上沉积第二金属层。 描述MIM电容器及其制造方法，其中MIM电容器与BEOL互连同时形成，并且以低成本制造大密度MIM电容器。

公开(公告)号：US20070235806A1

公开(公告)日：2007-10-11

申请号：US11279063

申请日：2006-04-07

申请人： Rajiv Joshi ,  Louis Hsu ,  Oleg Gluschenkov

发明人： Rajiv Joshi ,  Louis Hsu ,  Oleg Gluschenkov

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

公开(公告)号：US20070202637A1

公开(公告)日：2007-08-30

申请号：US11742147

申请日：2007-04-30

申请人： Jack Mandelman ,  Louis Hsu ,  Rajiv Joshi

发明人： Jack Mandelman ,  Louis Hsu ,  Rajiv Joshi

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/1203 ,  H01L29/94

摘要： A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

摘要翻译： 提供一种具有体电容板的半导体结构，其形成有确保体电容板与源极线（SL）扩散和位线扩散两者自对准的工艺。 因此，SL和位线扩散和体电容板之间的重叠量被精确地控制。 更具体地说，本发明通过使用确保存在1）板和源极/漏极扩散之间的最小重叠的过程形成具有侧壁电容器板的1T无电容的SOI体电荷存储单元的结构，以及2）最小重叠 在本发明中获得的精确控制并且不受对准公差的影响。 与现有技术相比，本发明的电池产生更大的信号余量，改善的性能，更小的芯片尺寸和降低的动态功耗。