Cache used both as cache and staging buffer
    1.
    发明授权
    Cache used both as cache and staging buffer 有权
    缓存用作缓存和分段缓冲区

    公开(公告)号:US08176257B2

    公开(公告)日:2012-05-08

    申请号:US13087974

    申请日:2011-04-15

    IPC分类号: G06F13/00 G06F12/00

    摘要: In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.

    摘要翻译: 在一个实施例中,高速缓存包括包括多个数据条目的数据存储器,每个数据条目具有存储高速缓存数据块的能力,以及耦合到数据存储器的高速缓存控制单元。 高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块,或者存储不是高速缓存的数据,而是正在高速缓存耦合到的接口上进行重传。

    Non-blocking address switch with shallow per agent queues
    2.
    发明授权
    Non-blocking address switch with shallow per agent queues 有权
    非阻塞地址开关,每个代理队列较浅

    公开(公告)号:US07970970B2

    公开(公告)日:2011-06-28

    申请号:US12787865

    申请日:2010-05-26

    IPC分类号: G06F13/00

    CPC分类号: G06F13/362 G06F13/4022

    摘要: In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

    摘要翻译: 在一个实施例中,开关被配置为耦合到互连。 开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。 多个存储位置被配置为存储由多个代理发送的多个请求。 仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。 所选择的请求是仲裁的赢家,并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。 在另一个实施例中,系统包括多个代理,互连和耦合到多个代理和互连的开关。 在另一个实施例中,预期了一种方法。

    Dual access pathways to serially-connected mass data storage units
    3.
    发明授权
    Dual access pathways to serially-connected mass data storage units 有权
    串行连接的大容量数据存储单元的双通道

    公开(公告)号:US07861107B1

    公开(公告)日:2010-12-28

    申请号:US12506887

    申请日:2009-07-21

    IPC分类号: G06F11/00

    摘要: A group of data storage units are serially connected in a sequential data communication path to communicate read and write operations to first and second interfaces of each data storage unit in the group. A data management computer device (“filer”) manages read and write operations of the data storage units of the group through an adapter of the filer. Main and redundant primary communication pathway connectors extend from the filer to the interfaces of the data storage unit, thereby establishing redundancy through multiple pathways to communicate the read and write operations to the data storage units of the group. Main and redundant secondary communication pathway connectors extend from partner filers to the groups of data storage units associated with each partner filer, thereby further enhancing redundancy.

    摘要翻译: 一组数据存储单元在顺序数据通信路径中串行连接,以将读取和写入操作传送到组中每个数据存储单元的第一和第二接口。 数据管理计算机设备(“filer”)通过文件管理器的适配器来管理该组的数据存储单元的读和写操作。 主要和冗余的主要通信路径连接器从文件管理器延伸到数据存储单元的接口,从而通过多个路径建立冗余,以将读取和写入操作传达到组的数据存储单元。 主要和冗余的二次通信路径连接器从伙伴文件管理器延伸到与每个合作伙伴文件管理器相关联的数据存储单元组,从而进一步增强冗余。

    Segmented interconnect for connecting multiple agents in a system
    4.
    发明授权
    Segmented interconnect for connecting multiple agents in a system 有权
    用于连接系统中多个代理的分段互连

    公开(公告)号:US07269682B2

    公开(公告)日:2007-09-11

    申请号:US11201573

    申请日:2005-08-11

    摘要: In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.

    摘要翻译: 在各种实施例中,装置包括多个代理和互连。 在一个实施方案中,多种试剂包括第一至第四试剂。 互连包括可切换的多个段(例如,使用多个选择电路)以形成代理之间的通信路径,并且第一段包括在从第一代理到第二代理的第一通信路径中,并且还 包括在从第三代理到第四代理的第二通信路径中。 在另一实施例中,每个段由选择电路驱动。 至少一个选择电路具有至少一个段和来自至少一个代理的输出作为输入。 在另一个实施例中,仲裁器被配置为确定每个请求代理在该互连上的通信路径到该段上的目的地代理。 仲裁器被配置为在对应的通信路径中的每个段可用的请求的子集之间进行仲裁。

    Cache used both as cache and staging buffer
    5.
    发明授权
    Cache used both as cache and staging buffer 有权
    缓存用作缓存和分段缓冲区

    公开(公告)号:US07624235B2

    公开(公告)日:2009-11-24

    申请号:US11565391

    申请日:2006-11-30

    IPC分类号: G06F13/00 G06F12/00

    摘要: In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.

    摘要翻译: 在一个实施例中,高速缓存包括包括多个数据条目的数据存储器,每个数据条目具有存储高速缓存数据块的能力,以及耦合到数据存储器的高速缓存控制单元。 高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块,或者存储不是高速缓存的数据,而是正在高速缓存耦合到的接口上进行重传。

    Non-blocking Address Switch with Shallow Per Agent Queues
    6.
    发明申请
    Non-blocking Address Switch with Shallow Per Agent Queues 有权
    非阻塞地址交换机与每个代理队列相邻

    公开(公告)号:US20090055568A1

    公开(公告)日:2009-02-26

    申请号:US12263255

    申请日:2008-10-31

    IPC分类号: G06F13/14

    CPC分类号: G06F13/362 G06F13/4022

    摘要: In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

    摘要翻译: 在一个实施例中,开关被配置为耦合到互连。 开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。 多个存储位置被配置为存储由多个代理发送的多个请求。 仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。 所选择的请求是仲裁的赢家,并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。 在另一个实施例中,系统包括多个代理,互连和耦合到多个代理和互连的开关。 在另一个实施例中,预期了一种方法。

    Coordinated shared storage architecture
    7.
    发明授权
    Coordinated shared storage architecture 有权
    协调共享存储架构

    公开(公告)号:US08180855B2

    公开(公告)日:2012-05-15

    申请号:US11075619

    申请日:2005-03-08

    IPC分类号: G06F15/16

    摘要: The present invention provides a novel coordinated shared storage architecture that permits the amortization of cost of the spares over any number of the storage systems and enables improvements to a number of storage system operations. The coordinated shared storage architecture comprises a plurality of storage systems disk shelves via a plurality of intermediate network devices, such as hubs. Each storage system includes a storage operating system having a target device driver module. The target device driver module permits the storage system to function as a SCSI target and thereby receive and process commands directed to it from other storage systems.

    摘要翻译: 本发明提供了一种新颖的协调共享存储架构,其允许在任何数量的存储系统上分摊备件的成本,并且能够改进多个存储系统操作。 协调的共享存储架构包括经由诸如集线器的多个中间网络设备的多个存储系统盘架。 每个存储系统包括具有目标设备驱动器模块的存储操作系统。 目标设备驱动器模块允许存储系统用作SCSI目标,从而从其他存储系统接收和处理指向它的命令。

    Non-blocking address switch with shallow per agent queues
    8.
    发明授权
    Non-blocking address switch with shallow per agent queues 有权
    非阻塞地址切换,每个代理队列较浅

    公开(公告)号:US07752366B2

    公开(公告)日:2010-07-06

    申请号:US12263255

    申请日:2008-10-31

    IPC分类号: G06F13/00

    CPC分类号: G06F13/362 G06F13/4022

    摘要: In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

    摘要翻译: 在一个实施例中,开关被配置为耦合到互连。 开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。 多个存储位置被配置为存储由多个代理发送的多个请求。 仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。 所选择的请求是仲裁的赢家,并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。 在另一个实施例中,系统包括多个代理,互连和耦合到多个代理和互连的开关。 在另一个实施例中,预期了一种方法。

    Cache Used Both as Cache and Staging Buffer
    9.
    发明申请
    Cache Used Both as Cache and Staging Buffer 有权
    缓存用作缓存和分段缓冲区

    公开(公告)号:US20100017568A1

    公开(公告)日:2010-01-21

    申请号:US12566609

    申请日:2009-09-24

    IPC分类号: G06F12/08 G06F12/00

    摘要: In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.

    摘要翻译: 在一个实施例中,高速缓存包括包括多个数据条目的数据存储器,每个数据条目具有存储高速缓存数据块的能力,以及耦合到数据存储器的高速缓存控制单元。 高速缓存控制单元被配置为动态地分配数据存储器中的给定数据条目以存储被缓存的高速缓存块,或者存储不是高速缓存的数据,而是正在高速缓存耦合到的接口上进行重传。

    Dual access pathways to serially-connected mass data storage units
    10.
    发明授权
    Dual access pathways to serially-connected mass data storage units 有权
    串行连接的大容量数据存储单元的双通道

    公开(公告)号:US07594134B1

    公开(公告)日:2009-09-22

    申请号:US11503716

    申请日:2006-08-14

    IPC分类号: G06F11/00

    摘要: A group of data storage units are serially connected in a sequential data communication path to communicate read and write operations to first and second interfaces of each data storage unit in the group. A data management computer device (“filer”) manages read and write operations of the data storage units of the group through an adapter of the filer. Main and redundant primary communication pathway connectors extend from the filer to the interfaces of the data storage unit, thereby establishing redundancy through multiple pathways to communicate the read and write operations to the data storage units of the group. Main and redundant secondary communication pathway connectors extend from partner filers to the groups of data storage units associated with each partner filer, thereby further enhancing redundancy.

    摘要翻译: 一组数据存储单元在顺序数据通信路径中串行连接,以将读取和写入操作传送到组中每个数据存储单元的第一和第二接口。 数据管理计算机设备(“filer”)通过文件管理器的适配器来管理该组的数据存储单元的读和写操作。 主要和冗余的主要通信路径连接器从文件管理器延伸到数据存储单元的接口,从而通过多个路径建立冗余,以将读取和写入操作传达到组的数据存储单元。 主要和冗余的二次通信路径连接器从伙伴文件管理器延伸到与每个合作伙伴文件管理器相关联的数据存储单元组,从而进一步增强冗余。