公开(公告)号：US4084152A

公开(公告)日：1978-04-11

申请号：US784744

申请日：1977-04-04

申请人： Gerald Bernard Long ,  Ralph Charles Mitchell ,  Shing Chou Pi

发明人： Gerald Bernard Long ,  Ralph Charles Mitchell ,  Shing Chou Pi

IPC分类号： H01L27/112 ,  H03K19/177 ,  G11C11/40 ,  H03K19/08

CPC分类号： H03K19/17712 ,  H01L27/112

摘要： This specification describes arrays for performing logic functions. In these arrays input variables are placed on a series of parallel input lines that intersect a number of parallel output lines in a grid of intersections. Field effect devices at these intersections have their gate terminals connected to one of the input lines and their source terminal connected to one of the output lines and through a load device to a source of potential. The drain terminals of these devices are either unconnected, connected directly to ground or connected to ground through one of two switching devices. The devices with unconnected drains are inoperative. The devices with their drains connected directly to ground are operative at all times. While the devices connected to ground through one of the switches are operative only when the switch is closed. The array can be time shared by two different logic functions by having one or the other of the switches off at any given time.

公开(公告)号：US3991408A

公开(公告)日：1976-11-09

申请号：US527777

申请日：1974-11-27

申请人： Arthur Wilbert Holmes, Jr. ,  Gerald Bernard Long ,  Richard Charles Paddock ,  Shing Chou Pi ,  Donald Walter Price

发明人： Arthur Wilbert Holmes, Jr. ,  Gerald Bernard Long ,  Richard Charles Paddock ,  Shing Chou Pi ,  Donald Walter Price

IPC分类号： G06F9/26 ,  G11C8/04 ,  G11C17/12 ,  G06F9/06 ,  G11C5/06 ,  G11C17/00

CPC分类号： G06F9/262 ,  G11C17/12 ,  G11C8/04

摘要： A self-sequenced read only memory is shown wherein each word line contains dynamic logic circuits for energizing a next word line after the fixed time delay provided by the dynamic logic circuits. Self-sequencing inverters are physically placed within the array area thereby increasing reliability and reducing circuit wiring. When used as a microprogram control storage, the memory is divided into a plurality of self-sequenced control routines. When a certain function is to be performed, the first word line of the control routine for performing the selected function is energized. Since each word line includes a one cycle delay and is wired to the next sequential word line, no separate timing or address control is required to address word lines within a selected control routine. Once a control routine is energized, sequential microinstructions will be automatically fetched including branch and branch-on condition instructions. Branch operations can be implemented by connecting one of the outputs of the array to the branched-to word line. Branch-on condition can be implemented by gating the inverter in the branched-to instruction with an AND circuit. By virtue of the self-sequencing of the memory, branched-to word lines can be sequentially accessing memory words simultaneously with sequential memory word fetch operations within the branched from control routine. The branched-to control routine thereby acts as a modifier routine to modify the bit patterns of the memory words which continue to be fetched by the branched-from control routine.

摘要翻译： 示出了自排序的只读存储器，其中每个字线包含用于在由动态逻辑电路提供的固定时间延迟之后激励下一字线的动态逻辑电路。 自定序逆变器物理放置在阵列区域内，从而提高可靠性并减少电路布线。 当用作微程序控制存储器时，存储器被分成多个自定序控制程序。 当要执行某个功能时，用于执行所选功能的控制程序的第一字线被通电。 由于每个字线包括一个周期延迟并且被连接到下一个顺序字线，所以不需要单独的定时或地址控制来对所选择的控制程序中的字线进行寻址。 一旦控制程序通电，将自动获取连续的微指令，包括分支和分支条件指令。 分支操作可以通过将阵列的一个输出连接到分支字线来实现。 可以通过使用AND电路在分支指令中选通逆变器来实现分支状态。 借助于存储器的自定序，分支到字线可以与从分支控制程序中的顺序存储器字提取操作同时顺序地访问存储器字。 因此，分支到控制例程用作修改程序，以修改由分支控制程序继续获取的存储器字的位模式。