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    Signal processing circuit, low-voltage signal generator and image display incorporating the same
    1.
    发明授权
    Signal processing circuit, low-voltage signal generator and image display incorporating the same 有权
    信号处理电路，低压信号发生器和包含其的图像显示

    公开(公告)号：US07978169B2

    公开(公告)日：2011-07-12

    申请号：US12071529

    申请日：2008-02-21

    申请人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

    发明人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G2310/0289 ,  G09G2330/021

    摘要： There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

    摘要翻译： 提供：第一逻辑运算电路，其使用高幅度逻辑信号执行逻辑运算; 具有负载电容的传输系统; 以及作为降压电平移位器的低压信号发生器，其将来自第一逻辑运算电路的输入高幅度逻辑信号变换为具有比高幅度逻辑信号更低的振幅的低幅度逻辑信号，以输出到 传输系统。 在该结构中，第一逻辑运算电路基于高幅度逻辑信号进行动作，因此没有故障，高速运转。 此外，引入负载电容的传输系统发送低幅度逻辑信号，因此抑制电力消耗的增加和不必要的辐射的发生。

    Shift register and image display apparatus using the same
    3.
    发明授权
    Shift register and image display apparatus using the same 有权
    移位寄存器和使用其的图像显示装置

    公开(公告)号：US06909417B2

    公开(公告)日：2005-06-21

    申请号：US09578440

    申请日：2000-05-25

    申请人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

    发明人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

    IPC分类号： G11C19/00 ,  G09G3/20 ,  G09G3/36

    CPC分类号： G09G3/3688 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2330/021

    摘要： A level shifter 13 is provided for each of SR flip flops F1 constituting a shift register 11. The level shifter 13 increases a voltage of a clock signal CK. This arrangement reduces a distance for transmitting a clock signal whose voltage has been increased, as compared with a construction in which a voltage of a clock signal is increased by a single level shifter and the signal is transmitted to each of the flip flops; consequently, a load capacity of the level shifter can be smaller. Furthermore, each of the level shifters is operated during a pulse output of the previous level shifter 13, and the operation is suspended at the end of the pulse output. Thus, the level shifters 13 can operate only when it is necessary to apply a clock signal CK to the corresponding SR flip flop F1. As a result, even when an amplitude of a clock signal is small, it is possible to reduce power consumption of the shift resister under normal operation.

    摘要翻译： 为构成移位寄存器11的每个SR触发器F 1提供电平移位器13.电平移位器13增加时钟信号CK的电压。 与通过单个电平移位器增加时钟信号的电压并且将信号发送到每个触发器的结构相比，这种布置减少了用于传输电压已经增加的时钟信号的距离; 因此，电平转换器的负载能力可以更小。 此外，每个电平移位器在先前电平移位器13的脉冲输出期间操作，并且在脉冲输出结束时暂停操作。 因此，只有当需要对相应的SR触发器F 1施加时钟信号CK时，电平移位器13才能够工作。结果，即使当时钟信号的幅度小时，也可以降低功耗 的正常运行中的移位寄存器。

    Active matrix devices
    4.
    发明授权
    Active matrix devices 失效
    主动矩阵设备

    公开(公告)号：US06437767B1

    公开(公告)日：2002-08-20

    申请号：US09054949

    申请日：1998-04-03

    申请人： Graham Andrew Cairns ,  Michael James Brownlow ,  Andrew Kay

    发明人： Graham Andrew Cairns ,  Michael James Brownlow ,  Andrew Kay

    IPC分类号： G09G336

    CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G3/3666

    摘要： An active matrix device includes a data line driver circuit for sampling the input signal to produce data signals for each of the rows of control elements in a corresponding line period, and a scan line driver circuit for addressing the scan lines sequentially by applying a scan signal to the scan inputs of the control elements along each of the rows so as to supply said data signals to the control elements along the row. Such circuits are controlled so that a data input signal is sampled and stored to produce data signals for a first group of the control elements along the row in a first line subperiod and the stored data signals are applied to the first group of control elements in a second line subperiod, and so that the data input signal is sampled and stored to produce data signals for a second group of control elements along the row in the second line subperiod and the stored data signals are applied to the second group of control elements in a subsequent line subperiod.

    摘要翻译： 有源矩阵装置包括数据线驱动器电路，用于对输入信号进行采样，以在相应的行周期内为每行控制元件产生数据信号;以及扫描线驱动电路，用于通过施加扫描信号来顺序寻址扫描线 到沿着每行的控制元件的扫描输入，以便将所述数据信号提供给沿着该行的控制元件。 这样的电路被控制，使得数据输入信号被采样和存储，以产生沿着第一行子周期中的行的第一组控制元件的数据信号，并且存储的数据信号被施加到第一组控制元件 并且使得数据输入信号被采样和存储以产生沿着第二行次周期中的行的第二组控制元件的数据信号，并且将存储的数据信号施加到第二组控制元件 后续行周期

    Fault tolerant circuit arrangement and active matrix device incorporating the same
    5.
    发明授权
    Fault tolerant circuit arrangement and active matrix device incorporating the same 失效
    容错电路布置和包含其的有源矩阵器件

    公开(公告)号：US6060941A

    公开(公告)日：2000-05-09

    申请号：US37909

    申请日：1998-03-10

    申请人： Michael James Brownlow ,  Andrew Kay ,  Graham Andrew Cairns

    发明人： Michael James Brownlow ,  Andrew Kay ,  Graham Andrew Cairns

    IPC分类号： G02F1/136 ,  G02F1/1368 ,  G09F9/00 ,  G09G3/20 ,  G09G3/36 ,  G06F11/16

    CPC分类号： G09G3/3688 ,  G09G2330/08

    摘要： A fault tolerant circuit arrangement includes: an input; an output; a first circuit element, a second circuit element, a third circuit element, and a fourth circuit element, provided in such a manner that the first and second circuit elements are connected in series between the input and the output to form a first series combination, and the third and fourth circuit elements are connected in series between the input and the output to form a second series combination, the first series combination being connected in parallel with the second series combination between the input and the output; and, a control element connected between an interconnection point of the first and second circuit elements and an interconnection point of the third and fourth circuit elements. The control element is switchable by a control signal between a conducting mode in which current flow is enabled between the interconnection points and a non-conducting mode in which current flow is prevented between the interconnection points.

    摘要翻译： 容错电路布置包括：输入; 输出 第一电路元件，第二电路元件，第三电路元件和第四电路元件，其设置成使得第一和第二电路元件串联连接在输入和输出之间以形成第一串联组合， 并且第三和第四电路元件串联在输入和输出之间以形成第二串联组合，第一串联组合与输入和输出之间的第二串联组合并联连接; 以及连接在第一和第二电路元件的互连点与第三和第四电路元件的互连点之间的控制元件。 控制元件可通过控制信号切换，该控制信号在互连点之间启用电流的导通模式与在互连点之间防止电流流动的非导通模式之间。

    Fault tolerant circuit arrangements
    6.
    发明授权
    Fault tolerant circuit arrangements 失效
    容错电路布置

    公开(公告)号：US5923512A

    公开(公告)日：1999-07-13

    申请号：US41394

    申请日：1998-03-12

    申请人： Michael James Brownlow ,  Andrew Kay ,  Graham Andrew Cairns ,  Toshio Nomura

    发明人： Michael James Brownlow ,  Andrew Kay ,  Graham Andrew Cairns ,  Toshio Nomura

    IPC分类号： G01R31/00 ,  G02F1/133 ,  G06F11/07 ,  G09G3/20 ,  G09G3/36 ,  H02H3/18

    CPC分类号： G06F11/2215 ,  H03K19/00392

    摘要： A fault tolerant circuit arrangement comprises a plurality of replicated non-redundant shift registers 30 connected in parallel and each having an enable/configuration input 31 and a plurality of outputs 36. Furthermore each register 30 includes a verify output 32 for outputting a verify signal indicating whether or not a fault condition is present within the register. The arrangement also includes a verification signal generator 33 for applying a fixed reference signal, a comparator 34 to which the verify signals from the outputs 32 are applied, and a control circuit 35. The test/control-logic of the comparator 34 and control circuit 35 is constructed using masking redundancy 20-24 in order to render the test/control logic tolerant to faults. The control circuit 35 serves to control testing of each of the registers 30 in turn by supplying an enable signal to the input 31 of each register 30 beginning with the first register. This causes the supply of a verify signal V.sub.1 from the verify output 32 of the first register 30 to the comparator 34 which compares the verify signal V.sub.1 to the reference signal. If the verify signal V.sub.1 is significantly different from the reference signal, this indicates that there is a fault present in the first register, and the control circuit 35 is caused to supply a disable signal to the input 31 of the first register. The test procedure is repeated for each register 30 until a verify signal is received by the comparator 34 which indicates that there is no fault present in the associated register.

    摘要翻译： 容错电路装置包括并联连接的多个复制非冗余移位寄存器30，每一个具有使能/配置输入31和多个输出36.此外，每个寄存器30包括验证输出32，用于输出指示 无论寄存器内是否存在故障状况。 该装置还包括用于施加固定参考信号的验证信号发生器33，来自输出端32的验证信号的施加的比较器34以及控制电路35.比较器34和控制电路的测试/控制逻辑 35使用掩蔽冗余20-24构造，以便使测试/控制逻辑容忍故障。 控制电路35用于依次通过从第一寄存器开始向每个寄存器30的输入端31提供使能信号来控制每个寄存器30的测试。 这导致将验证信号V1从第一寄存器30的验证输出32提供给比较器34，比较器34将验证信号V1与参考信号进行比较。 如果验证信号V1与参考信号显着不同，则表示第一寄存器中存在故障，并且使控制电路35向第一寄存器的输入端31提供禁止信号。 对于每个寄存器30重复测试程序，直到比较器34接收到验证信号，其指示相关联的寄存器中不存在故障。

    Drive Circuit, A Display Device Provided With The Same
    7.
    发明申请
    Drive Circuit, A Display Device Provided With The Same 有权
    驱动电路，具有该驱动电路的显示装置

    公开(公告)号：US20090002357A1

    公开(公告)日：2009-01-01

    申请号：US12087870

    申请日：2007-01-29

    申请人： Gareth John ,  Patrick Zebedee ,  Michael James Brownlow ,  Tim Gasser ,  Jeremy Lock ,  Graham Andrew Cairns ,  Jaganath Rajendra ,  Harry Garth Walton

    发明人： Gareth John ,  Patrick Zebedee ,  Michael James Brownlow ,  Tim Gasser ,  Jeremy Lock ,  Graham Andrew Cairns ,  Jaganath Rajendra ,  Harry Garth Walton

    IPC分类号： G09G5/00

    CPC分类号： H03K17/063 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G11C19/184

    摘要： In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.

    摘要翻译： 在本发明的一个实施例中，驱动电路包括：连接在第一电压源和第二电压源之间的逻辑块，以及包括多个采样电路的采样器。 每个采样电路用于在使用中对输入数据信号进行采样，并将电压输出到相应的输出。 驱动电路还包括具有多个升压电路的升压电路，每个升压电路与相应的一个采样电路相关联，并且在使用中产生升压电压信号并将升压电压信号提供给相应的采样电路 。 每个升压电路连接在第一电压源和第二电压源之间。 逻辑块可以是但不限于移位寄存器。

    Shift register and image display device
    8.
    发明授权
    Shift register and image display device 有权
    移位寄存器和图像显示设备

    公开(公告)号：US07212184B2

    公开(公告)日：2007-05-01

    申请号：US10800352

    申请日：2004-03-12

    申请人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

    发明人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2310/0289

    摘要： In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. Moreover, two kinds of clock signals, each of which has a duty ratio of not more than 50% and which have no overlapped portions in their low-level periods, are used so as to prevent the outputs of the shift-register from overlapping each other. Thus, it is possible to provide a shift register which is preferably used for a driving circuit of an image display device, can miniaturize the driving circuit, and can desirably change the pulse width of the output signal, and also to provide an image display device using such a shift register.

    摘要翻译： 在设置有与时钟信号同步工作的触发器的移位寄存器中，并且响应于每个触发器的前级的输出而被打开和关闭的开关装置被安装。 时钟信号由切换装置选择性地输入，所选择的时钟信号被反相并用作从每个级输出的移位寄存器。 此外，使用两种时钟信号，每个时钟信号的占空比不大于50％，并且在其低电平时段中没有重叠部分，以便防止移位寄存器的输出与每个 其他。 因此，可以提供优选用于图像显示装置的驱动电路的移位寄存器，可以使驱动电路小型化，并且可以期望地改变输出信号的脉冲宽度，并且还提供图像显示装置 使用这种移位寄存器。