公开(公告)号：US08354990B2

公开(公告)日：2013-01-15

申请号：US12087870

申请日：2007-01-29

申请人： Gareth John ,  Patrick Zebedee ,  Michael James Brownlow ,  Tim Gasser ,  Jeremy Lock ,  Graham Andrew Cairns ,  Jaganath Rajendra ,  Harry Garth Walton

发明人： Gareth John ,  Patrick Zebedee ,  Michael James Brownlow ,  Tim Gasser ,  Jeremy Lock ,  Graham Andrew Cairns ,  Jaganath Rajendra ,  Harry Garth Walton

IPC分类号： G09G3/36

CPC分类号： H03K17/063 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G11C19/184

摘要： In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.

摘要翻译： 在本发明的一个实施例中，驱动电路包括：连接在第一电压源和第二电压源之间的逻辑块，以及包括多个采样电路的采样器。 每个采样电路用于在使用中对输入数据信号进行采样，并将电压输出到相应的输出。 驱动电路还包括具有多个升压电路的升压电路，每个升压电路与相应的一个采样电路相关联，并且在使用中产生升压电压信号并将升压电压信号提供给相应的采样电路 。 每个升压电路连接在第一电压源和第二电压源之间。 逻辑块可以是但不限于移位寄存器。

公开(公告)号：US20090002357A1

公开(公告)日：2009-01-01

申请号：US12087870

申请日：2007-01-29

申请人： Gareth John ,  Patrick Zebedee ,  Michael James Brownlow ,  Tim Gasser ,  Jeremy Lock ,  Graham Andrew Cairns ,  Jaganath Rajendra ,  Harry Garth Walton

发明人： Gareth John ,  Patrick Zebedee ,  Michael James Brownlow ,  Tim Gasser ,  Jeremy Lock ,  Graham Andrew Cairns ,  Jaganath Rajendra ,  Harry Garth Walton

IPC分类号： G09G5/00

CPC分类号： H03K17/063 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G11C19/184

摘要： In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.

摘要翻译： 在本发明的一个实施例中，驱动电路包括：连接在第一电压源和第二电压源之间的逻辑块，以及包括多个采样电路的采样器。 每个采样电路用于在使用中对输入数据信号进行采样，并将电压输出到相应的输出。 驱动电路还包括具有多个升压电路的升压电路，每个升压电路与相应的一个采样电路相关联，并且在使用中产生升压电压信号并将升压电压信号提供给相应的采样电路 。 每个升压电路连接在第一电压源和第二电压源之间。 逻辑块可以是但不限于移位寄存器。

公开(公告)号：US08604949B2

公开(公告)日：2013-12-10

申请号：US13283060

申请日：2011-10-27

申请人： Gareth John ,  Patrick Zebedee

发明人： Gareth John ,  Patrick Zebedee

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A serial-to-parallel converter which includes n input latching elements; k intermediate latching elements, and n output latching elements configured to sample outputs of the k intermediate latching elements and a remaining (n−k) input latching elements of the n input latching elements, respectively, after the nth data of the n successive data has been sampled by the nth input latching element and before the kth data of a next n successive data in the serial input data stream has been sampled by the kth input latching element, wherein the n input latching elements and the k intermediate latching elements are transparent for one state of their clock input, and n and k are positive integers, where n>k.

摘要翻译： 包括n个输入锁存元件的串并转换器; k个中间锁存元件和n个输出锁存元件，其被配置为在n个连续数据的第n个数据被采样之后分别采样k个中间锁存元件的输出和n个输入锁存元件的剩余（nk）个输入锁存元件 在第n个输入锁存元件之前并且在串行输入数据流中的下一个n个连续数据的第k个数据已被第k个输入锁存元件采样之前，其中n个输入锁存元件和k个中间锁存元件对于一个状态是透明的 的时钟输入，n和k是正整数，其中n> k。

公开(公告)号：US20100134476A1

公开(公告)日：2010-06-03

申请号：US12451917

申请日：2008-08-27

申请人： Patrick Zebedee ,  Gareth John

发明人： Patrick Zebedee ,  Gareth John

IPC分类号： G06F3/038 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/04 ,  G09G2330/021

摘要： In one embodiment of the present invention, a shift register includes a plurality of stages which are activated in sequence. Each stage includes a logic circuit controlling first and second output circuits. The first output circuit includes a first switch in the form of a transistor, which connects an output of the stage to receive a pulse width control signal when the stage is active. A second switch in the form of a transistor connects the stage output to receive an inactive signal level when the stage is inactive. The second output circuit comprises a third switch in the form of a transistor, which connects a further output to receive an active signal level when the stage is active. A fourth switch in the form of a transistor connects the further output to receive an inactive signal level when the stage is inactive. The further output of each stage is connected to the logic circuit of at least one adjacent stage, such as a reset input of a preceding stage and/or a set input of a succeeding stage.

摘要翻译： 在本发明的一个实施例中，移位寄存器包括依次被激活的多个级。 每个级包括控制第一和第二输出电路的逻辑电路。 第一输出电路包括晶体管形式的第一开关，当阶段有效时，该第一开关连接级的输出以接收脉冲宽度控制信号。 晶体管形式的第二个开关将阶段输出连接起来，以便在阶段无效时接收无效信号电平。 第二输出电路包括晶体管形式的第三开关，当阶段有效时，该第三开关连接另一输出端以接收有源信号电平。 当晶体管不活动时，晶体管形式的第四开关连接另外的输出以接收无效信号电平。 每个级的进一步的输出连接到至少一个相邻级的逻辑电路，例如前级的复位输入和/或后级的设定输入。

公开(公告)号：US08982015B2

公开(公告)日：2015-03-17

申请号：US12736144

申请日：2009-03-31

申请人： Gareth John ,  Patrick Zebedee

发明人： Gareth John ,  Patrick Zebedee

IPC分类号： G09G3/20 ,  G09G5/00 ,  G11C19/00 ,  G11C19/28 ,  G09G3/36

CPC分类号： G11C19/28 ,  G09G3/20 ,  G09G3/3674 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2340/0492

摘要： A shift register includes cascade-connected stages, each of which includes a data latch and an output stage. In at least one embodiment, the latch has a single data input which, in use, receives a date signal from a preceding or succeeding stage. The output stage includes a first switch, which passes a clock signal to the stage output when the output stage is activated by the latch. The output stage also comprises a second switch, which passes the lower supply voltage to the stage output when the output stage is inactive.

摘要翻译： 移位寄存器包括级联连接级，其中每一级包括数据锁存器和输出级。 在至少一个实施例中，锁存器具有单个数据输入，其在使用中从前一个或后续阶段接收日期信号。 输出级包括第一开关，当输出级被锁存器激活时，第一开关将时钟信号传递到级输出端。 输出级还包括第二开关，当输出级无效时，该开关将较低的电源电压传递到级输出端。

公开(公告)号：US20110007040A1

公开(公告)日：2011-01-13

申请号：US12736144

申请日：2009-03-31

申请人： Gareth John ,  Patrick Zebedee

发明人： Gareth John ,  Patrick Zebedee

IPC分类号： G09G5/00 ,  G11C19/28

CPC分类号： G11C19/28 ,  G09G3/20 ,  G09G3/3674 ,  G09G2300/0408 ,  G09G2310/0267 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2340/0492

摘要： A shift register includes cascade-connected stages, each of which includes a data latch and an output stage. In at least one embodiment, the latch has a single data input which, in use, receives a date signal from a preceding or succeeding stage. The output stage includes a first switch, which passes a clock signal to the stage output when the output stage is activated by the latch. The output stage also comprises a second switch, which passes the lower supply voltage to the stage output when the output stage is inactive.

摘要翻译： 移位寄存器包括级联连接级，其中每一级包括数据锁存器和输出级。 在至少一个实施例中，锁存器具有单个数据输入，其在使用中从前一个或后续阶段接收日期信号。 输出级包括第一开关，当输出级被锁存器激活时，第一开关将时钟信号传递到级输出端。 输出级还包括第二开关，当输出级无效时，该开关将较低的电源电压传递到级输出端。

公开(公告)号：US08654571B2

公开(公告)日：2014-02-18

申请号：US13347856

申请日：2012-01-11

申请人： Gareth John ,  Patrick Zebedee

发明人： Gareth John ,  Patrick Zebedee

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： B01L3/50273 ,  B01L2200/061 ,  B01L2200/0673 ,  B01L2200/143 ,  B01L2300/0645 ,  B01L2300/161 ,  B01L2400/0427 ,  G09G3/348 ,  G09G2300/0852 ,  G09G2356/00

摘要： A static random-access memory (SRAM) cell which includes: a sampling switch and a feedback switch; and a first inverter and a second inverter connected in series whereby an output of the first inverter is connected to an input of the second inverter. An input of the first inverter is connected to a data input of the SRAM cell via the sampling switch, and to a data output of the SRAM cell independent of the feedback switch, an output of the second inverter is connected to the input of the first inverter via the feedback switch, and first and second clock inputs of the SRAM cell are configured to control the sampling switch and the feedback switch, respectively.

摘要翻译： 一种静态随机存取存储器（SRAM）单元，包括：采样开关和反馈开关; 以及串联连接的第一反相器和第二反相器，其中第一反相器的输出连接到第二反相器的输入。 第一反相器的输入经由采样开关连接到SRAM单元的数据输入，并且独立于反馈开关连接到SRAM单元的数据输出，第二反相器的输出连接到第一反相器的输入端 逆变器经由反馈开关，并且SRAM单元的第一和第二时钟输入被配置为分别控制采样开关和反馈开关。

公开(公告)号：US08173000B1

公开(公告)日：2012-05-08

申请号：US13008091

申请日：2011-01-18

申请人： Benjamin James Hadwen ,  Adrian Marc Simon Jacobs ,  Jason Roderick Hector ,  Gareth John

发明人： Benjamin James Hadwen ,  Adrian Marc Simon Jacobs ,  Jason Roderick Hector ,  Gareth John

IPC分类号： G01N27/447 ,  G01N27/453

CPC分类号： B01L3/50273 ,  B01L2200/0673 ,  B01L2300/161 ,  B01L2400/0427 ,  G02B26/005 ,  G09G3/348 ,  G09G2300/0857 ,  G09G2310/068

摘要： An active matrix electrowetting on dielectric (AM-EWOD) device which includes a plurality of array elements configured to manipulate one or more droplets of fluid on an array, each of the array elements including a corresponding array element circuit. Each array element circuit includes a top substrate electrode and a drive electrode between which the one or more droplets may be positioned; circuitry configured to write data to the corresponding array element by selectively applying to the drive electrode either: (i) a time-varying voltage waveform V1 of amplitude VB and period t0; or (ii) a time-varying voltage waveform V2, the logical inverse of V1, and applying to the top substrate electrode the time-varying voltage waveform V2+Voffset, where Voffset represents an offset voltage signal which may have AC and/or DC components and may equal zero.

摘要翻译： 在电介质（AM-EWOD）装置上的有源矩阵电润湿，其包括多个阵列元件，其被配置为操纵阵列上的一个或多个液滴，每个阵列元件包括相应的阵列元件电路。 每个阵列元件电路包括顶部基板电极和驱动电极，在该驱动电极之间可以定位一个或多个液滴; 配置为通过选择性地向驱动电极施加数据到相应的阵列元件的电路：（i）振幅VB和周期t0的时变电压波形V1; 或者（ii）时变电压波形V2（V1的逻辑倒数），并向顶部衬底电极施加时变电压波形V2 + Voffset，其中Voffset表示可以具有AC和/或DC的偏移电压信号 组件可以等于零。

公开(公告)号：US06531469B1

公开(公告)日：2003-03-11

申请号：US09889805

申请日：2001-07-20

申请人： Jean-Pierre Rieu ,  Jean-François Patoiseau ,  Gareth John ,  Bruno Legrand ,  Yvan Verscheure

发明人： Jean-Pierre Rieu ,  Jean-François Patoiseau ,  Gareth John ,  Bruno Legrand ,  Yvan Verscheure

IPC分类号： C07D41712

CPC分类号： C07D413/12 ,  C07D417/12

摘要： The invention concerns novel substituted N-benzo(thia/oxa)zines-2-yl-1-arylalkyloxyalkyl-4-piperidinamine, their preparation and their therapeutic use. The invention concerns compounds of formula (1) wherein: X represents an oxygen or sulphur atom; Y represents either an alkylene radical, branched or not and containing 2 to 6 carbon atoms or a CH2—CH(OH)—CH2— radical. R represents a hydrogen, an alkyl radical, branched or not and containing 1 to 7 carbon atoms; R1 to R6, identical or different, represent a hydrogen, a saturated or unsaturated alkyl, branched or not and containing 1 to 5 carbon atoms, a saturated or unsaturated alkyloxy, branched or not and containing 1 to 5 carbon atoms, a halogeno, nitro, hydroxy, acyl or acyloxy group comprising 2 to 3 carbon atoms, an alkylamino group containing 1 to 5 carbon atoms, a trifluoro methyl or trifluoro methoxyl group; n is an integer ranging from 1 to 6 inclusively, and their pure, enantiomers or their mixtures, the therapeutically acceptable mineral and organic salts of the compounds of formula (1) and their possible hydrates.

摘要翻译： 本发明涉及新型取代的N-苯并（噻唑/氧杂）嗪-2-基-1-芳基烷氧基烷基-4-哌啶胺及其制备及其治疗用途。 本发明涉及式（1）的化合物，其中：X表示氧或硫原子; Y表示亚烷基，支链或不支链，含有2-6个碳原子或CH2-CH（OH）-CH2-基。 R表示氢，烷基，支链或不支链，含有1至7个碳原子; R 1至R 6相同或不同，表示氢，饱和或不饱和的烷基，支链或不含并且含有1至5个碳原子，饱和或不饱和烷氧基，支链或不具有1至5个碳原子，卤代，硝基 ，含有2〜3个碳原子的羟基，酰基或酰氧基，含1至5个碳原子的烷基氨基，三氟甲基或三氟甲氧基; n是1至6的整数，以及它们的纯的对映体或它们的混合物，式（1）化合物的治疗上可接受的矿物和有机盐及其可能的水合物。

公开(公告)号：US06583159B1

公开(公告)日：2003-06-24

申请号：US09889811

申请日：2001-07-20

申请人： Jean-François Patoiseau ,  Jean-Pierre Rieu ,  Gareth John ,  Bruno Legrand ,  Yvan Verscheure

发明人： Jean-François Patoiseau ,  Jean-Pierre Rieu ,  Gareth John ,  Bruno Legrand ,  Yvan Verscheure

IPC分类号： A61K31445

CPC分类号： C07D211/58

摘要： The invention concerns compounds of formula (I) wherein: R1 and R2, identical or different, represent a saturated or unsaturated alkyl radical, branched or not and containing 1 to 7 carbon atoms; R3 to R8, identical or different, represent a hydrogen, an alkyl branched or not and containing 1 to 5 carbon atoms, an acyloxy, branched or not and containing 1 to 5 carbon atoms, a halogeno, nitro, hydroxy, acyl or alkoxy group containing 1 to 5 carbon atoms, a dialkylamino group containing 1 to 5 carbon atoms, a trifluoromethyl or trifluoro methoxyl group; Z represents an oxygen or sulphur atom or methylene; m represents an integer between 0 and 4 inclusively; n represents an integer between 2 and 7 inclusively; and their pure enantiomers and mixtures, the therapeutically acceptable mineral or organic salts of the compounds of formula (I) and their possible hydrates.

摘要翻译： 本发明涉及式（I）的化合物，其中：R 1和R 2相同或不同，表示饱和或不饱和的烷基，分支或不具有1至7个碳原子; R3至R8相同或不同，表示氢，支链或不支链，含有1至5个碳原子的烷基，酰氧基，支链或不支化，含有1至5个碳原子，卤代，硝基，羟基，酰基或烷氧基 含有1至5个碳原子的二烷基氨基，含有1至5个碳原子的二烷基氨基，三氟甲基或三氟甲氧基; Z表示氧或硫原子或亚甲基; m表示0和4之间的整数; n表示2〜7的整数， 和它们的纯对映异构体和混合物，式（I）化合物的治疗上可接受的矿物或有机盐及其可能的水合物。