公开(公告)号：US08354990B2

公开(公告)日：2013-01-15

申请号：US12087870

申请日：2007-01-29

申请人： Gareth John ,  Patrick Zebedee ,  Michael James Brownlow ,  Tim Gasser ,  Jeremy Lock ,  Graham Andrew Cairns ,  Jaganath Rajendra ,  Harry Garth Walton

发明人： Gareth John ,  Patrick Zebedee ,  Michael James Brownlow ,  Tim Gasser ,  Jeremy Lock ,  Graham Andrew Cairns ,  Jaganath Rajendra ,  Harry Garth Walton

IPC分类号： G09G3/36

CPC分类号： H03K17/063 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G11C19/184

摘要： In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.

摘要翻译： 在本发明的一个实施例中，驱动电路包括：连接在第一电压源和第二电压源之间的逻辑块，以及包括多个采样电路的采样器。 每个采样电路用于在使用中对输入数据信号进行采样，并将电压输出到相应的输出。 驱动电路还包括具有多个升压电路的升压电路，每个升压电路与相应的一个采样电路相关联，并且在使用中产生升压电压信号并将升压电压信号提供给相应的采样电路 。 每个升压电路连接在第一电压源和第二电压源之间。 逻辑块可以是但不限于移位寄存器。

公开(公告)号：US20090002357A1

公开(公告)日：2009-01-01

申请号：US12087870

申请日：2007-01-29

申请人： Gareth John ,  Patrick Zebedee ,  Michael James Brownlow ,  Tim Gasser ,  Jeremy Lock ,  Graham Andrew Cairns ,  Jaganath Rajendra ,  Harry Garth Walton

发明人： Gareth John ,  Patrick Zebedee ,  Michael James Brownlow ,  Tim Gasser ,  Jeremy Lock ,  Graham Andrew Cairns ,  Jaganath Rajendra ,  Harry Garth Walton

IPC分类号： G09G5/00

CPC分类号： H03K17/063 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/0289 ,  G11C19/184

摘要： In one embodiment of the present invention, a drive circuit includes: a logic block connected between a source of a first voltage and a source of a second voltage, and a sampler including a plurality of sampling circuits. Each sampling circuit is for sampling, in use, an input data signal and outputting a voltage to a respective output. The drive circuit further includes a voltage booster having plurality of voltage boost circuits, each voltage boost circuit being associated with a respective one of the sampling circuits and, in use, generating a boosted voltage signal and providing the boosted voltage signal to the respective sampling circuit. Each voltage boost circuit is connected between the source of the first voltage and the source of the second voltage. The logic block may be, but is not limited to, a shift register.

摘要翻译： 在本发明的一个实施例中，驱动电路包括：连接在第一电压源和第二电压源之间的逻辑块，以及包括多个采样电路的采样器。 每个采样电路用于在使用中对输入数据信号进行采样，并将电压输出到相应的输出。 驱动电路还包括具有多个升压电路的升压电路，每个升压电路与相应的一个采样电路相关联，并且在使用中产生升压电压信号并将升压电压信号提供给相应的采样电路 。 每个升压电路连接在第一电压源和第二电压源之间。 逻辑块可以是但不限于移位寄存器。

公开(公告)号：US07217588B2

公开(公告)日：2007-05-15

申请号：US11178148

申请日：2005-07-08

申请人： John W. Hartzell ,  Harry Garth Walton ,  Michael James Brownlow

发明人： John W. Hartzell ,  Harry Garth Walton ,  Michael James Brownlow

IPC分类号： H01L21/00

CPC分类号： B81C1/0023 ,  H01L27/1214

摘要： An integrated MEMS package and associated packaging method are provided. The method includes: forming an electrical circuit, electrically connected to the first substrate; integrating a MEMS device on a first substrate region, electrically connected to the first substrate; providing a second substrate overlying the first substrate; and, forming a wall along the first region boundaries, between the first and second substrate. In one aspect, the electrical circuit is formed using thin-film processes; and, wherein integrating the MEMS device on the first substrate region includes forming the MEMS using thin-film processes, simultaneous with the formation of the electrical device. Alternately, the MEMS device is formed in a separate process, attached to the first substrate, and electrical interconnections are formed to the first substrate using thin-film processes.

摘要翻译： 提供集成MEMS封装和相关封装方法。 该方法包括：形成电连接到第一基板的电路; 将MEMS器件集成在电连接到第一衬底的第一衬底区域上; 提供覆盖所述第一基板的第二基板; 以及沿所述第一区域边界在所述第一和第二基板之间形成壁。 在一个方面，使用薄膜工艺形成电路; 并且其中将MEMS器件集成在第一衬底区域上包括使用薄膜工艺形成MEMS，同时形成电子器件。 或者，MEMS器件以独立的工艺形成，附接到第一衬底，并且使用薄膜工艺将电互连形成到第一衬底。

公开(公告)号：US20100194721A1

公开(公告)日：2010-08-05

申请号：US12094360

申请日：2006-09-01

申请人： Kazuhiko Miyata ,  Michael James Brownlow ,  Harry Garth Walton

发明人： Kazuhiko Miyata ,  Michael James Brownlow ,  Harry Garth Walton

IPC分类号： G09G5/10

CPC分类号： G09G3/2096 ,  G02F1/13452 ,  G02F2001/133612 ,  G06F3/14 ,  G09G3/3406 ,  G09G2320/0626 ,  G09G2360/145 ,  G09G2370/04 ,  G09G2370/08

摘要： A display device is provided, including a signal transmission mechanism that makes it possible to reduce the number of pins on an FPC board connected to a TFT substrate or eliminate the necessity for the FPC board, and that can be readily applied to a compact device.The present liquid crystal display device includes light detectors, a receiver circuit, a display control circuit, a video signal line drive circuit, a scanning signal line drive circuit, and a display portion, which are formed on a TFT substrate of a liquid crystal display panel, and it also includes white LEDs, and an LED drive circuit, which are included in a backlight portion. The LED drive circuit drives the white LEDs, each emitting a light (modulation) signal LS in accordance with an externally-provided video signal VS. The receiver circuit generates (demodulates) the video signal VS based on a signal received via the light detector. Such an optical transmission mechanism makes it possible to reduce the number of pins on the FPC board or eliminate the FPC board.

摘要翻译： 提供了一种显示装置，包括可以减少连接到TFT基板的FPC基板上的引脚数量或不需要FPC板的信号传输机构，并且可以容易地应用于紧凑的装置。 本液晶显示装置包括形成在液晶显示器的TFT基板上的光检测器，接收电路，显示控制电路，视频信号线驱动电路，扫描信号线驱动电路和显示部 面板，并且还包括白色LED和包括在背光部分中的LED驱动电路。 LED驱动电路驱动白色LED，每个白色LED根据外部提供的视频信号VS发射光（调制）信号LS。 接收器电路基于经由光检测器接收的信号来生成（解调）视频信号VS。 这样的光传输机构使得可以减少FPC板上的引脚数量或者消除FPC基板。

公开(公告)号：US07569410B2

公开(公告)日：2009-08-04

申请号：US11640592

申请日：2006-12-18

申请人： John W. Hartzell ,  Harry Garth Walton ,  Michael James Brownlow

发明人： John W. Hartzell ,  Harry Garth Walton ,  Michael James Brownlow

IPC分类号： H01L21/00

CPC分类号： B81C1/0023 ,  H01L27/1214

摘要： An integrated MEMS package and associated packaging method are provided. The method includes: forming an electrical circuit, electrically connected to the first substrate; integrating a MEMS device on a first substrate region, electrically connected to the first substrate; providing a second substrate overlying the first substrate; and, forming a wall along the first region boundaries, between the first and second substrate. In one aspect, the electrical circuit is formed using thin-film processes; and, wherein integrating the MEMS device on the first substrate region includes forming the MEMS using thin-film processes, simultaneous with the formation of the electrical device. Alternately, the MEMS device is formed in a separate process, attached to the first substrate, and electrical interconnections are formed to the first substrate using thin-film processes.

摘要翻译： 提供集成MEMS封装和相关封装方法。 该方法包括：形成电连接到第一基板的电路; 将MEMS器件集成在电连接到第一衬底的第一衬底区域上; 提供覆盖所述第一基板的第二基板; 以及沿所述第一区域边界在所述第一和第二基板之间形成壁。 在一个方面，使用薄膜工艺形成电路; 并且其中将MEMS器件集成在第一衬底区域上包括使用薄膜工艺形成MEMS，同时形成电子器件。 或者，MEMS器件以独立的工艺形成，附接到第一衬底，并且使用薄膜工艺将电互连形成到第一衬底。

公开(公告)号：US07042433B1

公开(公告)日：2006-05-09

申请号：US09567364

申请日：2000-05-09

申请人： Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Graham Andrew Cairns ,  Michael James Brownlow

发明人： Yasushi Kubota ,  Hajime Washio ,  Kazuhiro Maeda ,  Graham Andrew Cairns ,  Michael James Brownlow

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2310/0289

摘要： A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring. As a result, reduction of a parasitic capacitance of the wiring, reduction in the number of elements, reduction in the size of an amplitude of an input signal, etc. in the signal line driving circuit are attained.

摘要翻译： 信号线驱动电路包括具有多个移位电路的移位寄存器，每个移位电路将开始脉冲连续地移位到下一级，与时钟信号的定时同步。 在该信号线驱动电路中，基于两个相邻移位电路的输出脉冲，从与门输出移位脉冲。 同时，用于指定移位脉冲的脉冲宽度的宽度指定脉冲通过由移位脉冲控制其ON / OFF操作的晶体管输入。 逻辑运算电路对移位脉冲和宽度指定脉冲进行AND运算，并将运算结果输出到信号线。 当移位脉冲不起作用时，晶体管变为截止，使得将信号线发送宽度指定脉冲与信号线驱动电路断开，从而降低布线的容性负载。 结果，实现了信号线驱动电路中布线的寄生电容的减小，元件数目的减少，输入信号的幅度的减小等。

公开(公告)号：US06970163B2

公开(公告)日：2005-11-29

申请号：US10092372

申请日：2002-03-05

申请人： Graham Andrew Cairns ,  Michael James Brownlow

发明人： Graham Andrew Cairns ,  Michael James Brownlow

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  G09G5/18

CPC分类号： G09G3/20 ,  G09G3/3648 ,  G09G5/006 ,  G09G5/18 ,  G09G2300/0408 ,  G09G2320/0276 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2340/0435

摘要： A frame rate controller (20) is provided for controlling the frame refresh rate of an active matrix display. The controller (20) comprises a first circuit such as a preloadable synchronous counter (21) which counts vertical synchronization signals VSYNC and supplies an enable signal FE for every Nth frame of data, where N is an integer greater than zero and is selectable. A gating arrangement (26) is controlled by the enable signal FE so that an active matrix display is refreshed for every Nth frame of data, thus allowing a reduction in power consumption of the display.

摘要翻译： 提供了一种用于控制有源矩阵显示器的帧刷新率的帧速率控制器（20）。 控制器（20）包括第一电路，例如对可垂直同步信号VSYNC进行计数的预加载同步计数器（21），并为每第N个数据帧提供使能信号FE，其中N是大于零的整数并且是可选择的。 选通布置（26）由使能信号FE控制，使得对于每第N帧数据刷新有源矩阵显示，从而允许显示器的功耗降低。

公开(公告)号：US06445323B1

公开(公告)日：2002-09-03

申请号：US09943593

申请日：2001-08-30

申请人： Graham Andrew Cairns ,  Michael James Brownlow

发明人： Graham Andrew Cairns ,  Michael James Brownlow

IPC分类号： H03M166

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G2310/0248 ,  G09G2310/027 ,  G09G2320/0276 ,  G09G2330/021 ,  G09G2340/0428 ,  G09G2340/12 ,  G09G2340/125

摘要： Multi-format sampling registers, digital to analogue converters, data drivers and active matrix displays are provided which provide power saving in lower resolution formats by disabling circuitry which is not required in those formats.

公开(公告)号：US06404230B1

公开(公告)日：2002-06-11

申请号：US09803125

申请日：2001-03-09

申请人： Graham Andrew Cairns ,  Michael James Brownlow

发明人： Graham Andrew Cairns ,  Michael James Brownlow

IPC分类号： H03K190175

CPC分类号： H03K19/018521 ,  H03K19/09429

摘要： A level-shifting pass gate comprises a field effect transistor (M1) whose source is connected to a signal input (IN) and whose drain is connected to a signal output (OUT). A load (R) is connected between the drain of the transistor (M1) and a supply line (vdd). A control means (1) has an enable input (EN) which receives signals for enabling or disabling the pass gate. When the gate is enabled, the control means (1) controls the transistor (M1) and possibly the load (R) so that an input logic low level is passed substantially unchanged whereas a relatively low input high level is shifted to a higher output logic high level approaching the supply voltage. When the pass gate is disabled, the transistor (M1) is switched off so that the input (IN) is isolated from the output (OUT) and assumes a high impedance state. Conversely, when disabled, the output (OUT) defaults to a predetermined state, such as logic low, logic high or high impedance.

摘要翻译： 电平移动通过门包括其源极连接到信号输入（IN）并且其漏极连接到信号输出（OUT）的场效应晶体管（M1）。 负载（R）连接在晶体管（M1）的漏极和电源线（vdd）之间。 控制装置（1）具有使能输入（EN），其接收用于启用或禁用通过门的信号。 当门被使能时，控制装置（1）控制晶体管（M1）和可能的负载（R），使得输入逻辑低电平基本上不变，而相对低的输入高电平被转移到较高的输出逻辑 高电平接近电源电压。 当禁止通电门时，晶体管（M1）关闭，使得输入（IN）与输出（OUT）隔离并呈现高阻抗状态。 相反，当禁用时，输出（OUT）默认为预定状态，例如逻辑低电平，逻辑高电平或高阻抗。

公开(公告)号：US20080150924A1

公开(公告)日：2008-06-26

申请号：US12071529

申请日：2008-02-21

申请人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

发明人： Hidehiko Yamashita ,  Hajime Washio ,  Yasushi Kubota ,  Graham Andrew Cairns ,  Michael James Brownlow

IPC分类号： G06F3/038 ,  H03K19/0175

CPC分类号： G09G3/3688 ,  G09G3/20 ,  G09G2310/0289 ,  G09G2330/021

摘要： There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

摘要翻译： 提供：第一逻辑运算电路，其使用高幅度逻辑信号执行逻辑运算; 具有负载电容的传输系统; 以及作为降压电平移位器的低压信号发生器，其将来自第一逻辑运算电路的输入高幅度逻辑信号变换为具有比高幅度逻辑信号更低的振幅的低幅度逻辑信号，以输出到 传输系统。 在该结构中，第一逻辑运算电路基于高幅度逻辑信号进行动作，因此没有故障，高速运转。 此外，引入负载电容的传输系统发送低幅度逻辑信号，因此抑制电力消耗的增加和不必要的辐射的发生。