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    Circuitry for retiming a received data signal
    2.
    发明授权
    Circuitry for retiming a received data signal 失效
    重新定时接收数据信号的电路

    公开(公告)号：US5930311A

    公开(公告)日：1999-07-27

    申请号：US731154

    申请日：1996-10-10

    申请人： Gregory S. Lovelace ,  Amanda G. Noe ,  David M. Smith

    发明人： Gregory S. Lovelace ,  Amanda G. Noe ,  David M. Smith

    IPC分类号： G06F5/08 ,  H04L7/00

    CPC分类号： G06F5/08 ,  H04L7/0012

    摘要： A circuitry (10) is provided for automatically retiming a received synchronous data signal to a local clock. The circuitry (10) includes a first flip-flop (20) operable to register at least one synchronous data signal in response to a receive clock signal and to generate at least one data output signal. An OR gate (26) receives a data latch enable signal and a local clock signal. The local clock signal is frequency coherent with the receive clock signal. The OR gate (26) produces an enable signal. A latch (28) is coupled to the OR gate (26) for receiving the enable signal and in cascading arrangement with the first flip-flop (20). The latch (28) latches the data output signal on the falling edge of the local clock signal when the data latch enable signal is low. The latch (28) holds the latched data output signal as long as the local clock signal and the data latch enable signal are low. When either the local clock signal or the data latch enable signal is high, the latch (28) passes the data output signal. A second flip-flop (30), coupled in cascading arrangement with the latch (28), registers the data output signal passed through the latch (28) in response to the local clock signal. The signal output by the second flip-flop (30) is timed to the local clock signal.

    摘要翻译： 提供一个电路（10），用于将接收的同步数据信号自动重新定时到本地时钟。 电路（10）包括第一触发器（20），其可操作以响应于接收时钟信号来寄存至少一个同步数据信号并产生至少一个数据输出信号。 或门（26）接收数据锁存使能信号和本地时钟信号。 本地时钟信号与接收时钟信号频率一致。 或门（26）产生使能信号。 锁存器（28）耦合到或门（26），用于接收使能信号并与第一触发器（20）并联布置。 当数据锁存使能信号为低电平时，锁存器（28）锁存本地时钟信号的下降沿上的数据输出信号。 只要本地时钟信号和数据锁存使能信号为低，锁存器（28）保持锁存的数据输出信号。 当本地时钟信号或数据锁存使能信号为高时，锁存器（28）通过数据输出信号。 响应于本地时钟信号，与锁存器（28）以级联布置耦合的第二触发器（30）将通过锁存器（28）的数据输出信号进行寄存。 由第二触发器（30）输出的信号被定时到本地时钟信号。

    System and method for controlling timing in a distributed digital cross-connect system
    3.
    发明授权
    System and method for controlling timing in a distributed digital cross-connect system 失效
    用于控制分布式数字交叉连接系统中的定时的系统和方法

    公开(公告)号：US5901136A

    公开(公告)日：1999-05-04

    申请号：US774156

    申请日：1996-12-26

    申请人： Gregory S. Lovelace ,  Michael H. Jette ,  Steven D. Sensel ,  Edgar L. Read ,  Amanda G. Noe

    发明人： Gregory S. Lovelace ,  Michael H. Jette ,  Steven D. Sensel ,  Edgar L. Read ,  Amanda G. Noe

    IPC分类号： H04J3/06 ,  H04Q11/04 ,  H04J3/22 ,  H04L12/64

    CPC分类号： H04J3/0691 ,  H04Q11/04

    摘要： A timing system (100) for coordinating the components of a distributed digital cross-connect system (10) is provided. The timing system (100) includes a master timing system (102) that receives a network timing reference (98, 99) and generates a master timing signal. A distributed services node timing system (104, 106) is connected to the master timing system (102) and receives the master timing signal. The distributed services node timing system (104, 106) then embeds a timing signal in a data transmission frame (150). Two or more digital cross-connect timing systems (108) are connected to the distributed services node timing system (104, 106) and receive the data transmission frame (150). The digital cross-connect timing systems (108) retrieve the embedded timing signal from the data transmission frame (150).

    摘要翻译： 提供了一种用于协调分布式数字交叉连接系统（10）的组件的定时系统（100）。 定时系统（100）包括接收网络定时参考（98,99）并产生主定时信号的主定时系统（102）。 分布式业务节点定时系统（104,106）连接到主定时系统（102）并且接收主定时信号。 分布式业务节点定时系统（104,106）然后在数据传输帧（150）中嵌入定时信号。 两个或多个数字交叉连接定时系统（108）连接到分布式服务节点定时系统（104,106），并接收数据传输帧（150）。 数字交叉连接定时系统（108）从数据传输帧（150）检索嵌入的定时信号。