公开(公告)号：US06835985B2

公开(公告)日：2004-12-28

申请号：US09733836

申请日：2000-12-09

申请人： Jun Cai ,  Guang Ping Hua ,  Jun Song ,  Keng Foo Lo

发明人： Jun Cai ,  Guang Ping Hua ,  Jun Song ,  Keng Foo Lo

IPC分类号： H01L2362

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

公开(公告)号：US06555878B2

公开(公告)日：2003-04-29

申请号：US10233764

申请日：2002-09-03

申请人： Jun Song ,  Guang ping Hua ,  Keng-Foo Lo

发明人： Jun Song ,  Guang ping Hua ,  Keng-Foo Lo

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode). A latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide—similar to a field oxide—under the poly gate.

摘要翻译： 描述了具有用于IC器件中的ESD保护电路的U形门（UMOS）的MOS栅极控制SCR（UGSCR）结构，其与浅沟槽隔离（STI）和自对准硅化物（自对准硅）制造技术相兼容 。 UMOS门位于p基板中，并且被两侧的n阱包围。 邻近UMOS门的一侧，形成跨越第一n阱的第一n +扩散。 n +扩散以及旁边扩散的p +拾取器形成SCR（晶闸管）的阴极。 在UMOS门的另一侧附近，在第二n阱中形成第二n +和p +扩散。 第二个n +和p +扩散与UMOS门一起形成SCR的阳极和要保护的电路的输入端。 SCR由第一n +扩散/ n阱（阴极），p衬底，第二n阱和第二p + / n +扩散（阳极）形成。 闭锁免疫电路通过在聚栅下形成一个衬有厚栅极氧化物（类似于场氧化物）的U形门结构来实现。

公开(公告)号：US06458632B1

公开(公告)日：2002-10-01

申请号：US09814478

申请日：2001-03-14

申请人： Jun Song ,  Guang Ping Hua ,  Keng-Foo Lo

发明人： Jun Song ,  Guang Ping Hua ,  Keng-Foo Lo

IPC分类号： H01L21332

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： Described is a method of creating a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode). A latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide—similar to a field oxide—under the poly gate.

摘要翻译： 描述了一种用于在IC器件中的用于ESD保护电路的U形栅极（UMOS）的MOS栅极控制SCR（UGSCR）结构的方法，其与浅沟槽隔离（STI）和自对准硅化物（STI）兼容 自杀）制造技术。 UMOS门位于p基板中，并且被两侧的n阱包围。 邻近UMOS门的一侧，形成跨越第一n阱的第一n +扩散。 n +扩散以及旁边扩散的p +拾取器形成SCR（晶闸管）的阴极。 在UMOS门的另一侧附近，在第二n阱中形成第二n +和p +扩散。 第二个n +和p +扩散与UMOS门一起形成SCR的阳极和要保护的电路的输入端。 SCR由第一n +扩散/ n阱（阴极），p衬底，第二n阱和第二p + / n +扩散（阳极）形成。 闭锁免疫电路通过在聚栅下形成一个衬有厚栅极氧化物（类似于场氧化物）的U形门结构来实现。

公开(公告)号：US6027982A

公开(公告)日：2000-02-22

申请号：US245565

申请日：1999-02-05

申请人： Igor V. Peidous ,  Vladislav Y. Vassiliev ,  Chock H. Gan ,  Guang Ping Hua

发明人： Igor V. Peidous ,  Vladislav Y. Vassiliev ,  Chock H. Gan ,  Guang Ping Hua

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76235 ,  Y10S148/05

摘要： A method to form shallow trench isolation structures with improved isolation fill and surface planarity is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A thin oxide layer is deposited overlying the silicon nitride layer. An isolation trench is etched through the thin oxide layer, the nitride layer, and the pad oxide layer and into the substrate. The silicon nitride layer exposed within the trench is etched to form a lateral undercut leaving a projection of the thin oxide layer and exposing a portion of the underlying pad oxide layer. The thin oxide layer and the exposed portion of the pad oxide layer are etched away thereby exposing portions of the surface of the substrate. A liner oxide is grown on the exposed portions of the semiconductor substrate within the isolation trench and on the surface of the substrate. A layer of isolation dielectric is deposited overlying the liner oxide and the silicon nitride and filling the isolation trench. The isolation dielectric is polished away stopping at the silicon nitride layer. The remaining silicon nitride etched away. The isolation dielectric and the pad oxide are etched away from the surface of the semiconductor substrate. The fabrication of the integrated circuit device is completed.

摘要翻译： 描述了形成具有改进的隔离填充和表面平面性的浅沟槽隔离结构的方法。 衬垫氧化物层设置在半导体衬底的表面上。 在衬垫氧化物层上沉积氮化硅层。 沉积在氮化硅层上的薄氧化层。 通过薄氧化物层，氮化物层和焊盘氧化物层蚀刻隔离沟槽并进入衬底。 在沟槽内暴露的氮化硅层被蚀刻以形成横向底切，留下薄的氧化物层的突起，并暴露下面的衬垫氧化物层的一部分。 薄氧化物层和衬垫氧化物层的暴露部分被蚀刻掉，从而暴露衬底表面的部分。 衬垫氧化物生长在半导体衬底在隔离沟槽内和衬底表面上的暴露部分上。 沉积覆盖衬垫氧化物和氮化硅并且填充隔离沟槽的隔离电介质层。 在氮化硅层处停止隔离电介质被抛光。 剩余的氮化硅蚀刻掉。 绝缘电介质和衬垫氧化物被蚀刻离开半导体衬底的表面。 完成集成电路器件的制造。

公开(公告)号：US06855609B2

公开(公告)日：2005-02-15

申请号：US10670918

申请日：2003-09-24

申请人： Jun Cai ,  Guang Ping Hua ,  Jun Song ,  Keng Foo Lo

发明人： Jun Cai ,  Guang Ping Hua ,  Jun Song ,  Keng Foo Lo

IPC分类号： H01L27/02 ,  H01L21/336

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A transistor structure is manufactured for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

摘要翻译： 在集成电路器件中制造用于ESD保护的晶体管结构。 半导体衬底具有源极和漏极扩散区域以及源极和漏极扩散区域下的源极和漏极阱。 形成在半导体衬底上并进入半导体衬底的浅沟槽隔离件分离源极和漏极扩散区域以及源极和漏极阱的一部分。 源极和漏极接触结构分别形成在源极和漏极扩散区上的浅沟槽隔离上，并延伸穿过浅沟槽隔离以接触源极和漏极扩散区域。 通过接触开口进入离子注入到源阱和漏极的底部，以控制器件触发电压并将放电电流定位远离表面，从而显着提高器件ESD性能。