公开(公告)号：US20080057721A1

公开(公告)日：2008-03-06

申请号：US11847679

申请日：2007-08-30

申请人： Hyun-Ju Lim

发明人： Hyun-Ju Lim

IPC分类号： H01L21/311

CPC分类号： H01L21/76232 ,  Y10S148/05

摘要： A method of fabricating a semiconductor device including at least one of the following steps: forming an oxide layer on and/or over a silicon substrate. Forming a first photoresist pattern on and/or over the oxide layer. Forming a trench by etching the oxide layer and the substrate using the first photoresist pattern as a mask. Removing the first photoresist pattern. Filling the trench with a trench oxide layer. Planarizing the trench oxide layer. Forming an etch stop layer on and/or over the trench oxide layer. Forming a second photoresist pattern on and/or over the etch stop layer. Etching the etch stop layer and the trench oxide layer using the second photoresist pattern as an etch mask. Removing the second photoresist pattern and the etch stop layer.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤中的至少一个：在硅衬底上和/或之上形成氧化物层。 在氧化物层上和/或上方形成第一光致抗蚀剂图案。 通过使用第一光致抗蚀剂图案作为掩模蚀刻氧化物层和基板来形成沟槽。 去除第一光致抗蚀剂图案。 用沟槽氧化层填充沟槽。 平面化沟槽氧化层。 在沟槽氧化物层上和/或上方形成蚀刻停止层。 在蚀刻停止层上和/或上方形成第二光致抗蚀剂图案。 使用第二光致抗蚀剂图案蚀刻蚀刻停止层和沟槽氧化物层作为蚀刻掩模。 去除第二光致抗蚀剂图案和蚀刻停止层。

公开(公告)号：US06960818B1

公开(公告)日：2005-11-01

申请号：US09000626

申请日：1997-12-30

申请人： Rajesh Rengarajan ,  Venkatachalam C. Jaiprakash

发明人： Rajesh Rengarajan ,  Venkatachalam C. Jaiprakash

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L29/00

CPC分类号： H01L27/10861 ,  H01L21/76224 ,  Y10S148/05

摘要： A method for reducing hot carrier reliability problems within an integrated circuit device. The method includes forming a shallow trench isolation structure incorporated with the device by filling a trench with a photoresist plug and removing a portion of the photoresist plug to a level below the depth of a channel also incorporated with the device. A nitride liner disposed within the trench under the photoresist plug is then recessed to a level substantially equal to the level of the photoresist material, which is then removed. The method further includes the deposition of oxide fill within the trench, thereby encapsulating the recessed nitride liner.

摘要翻译： 一种降低集成电路装置内热载体可靠性问题的方法。 该方法包括通过用光致抗蚀剂插塞填充沟槽并且将光致抗蚀剂插塞的一部分移除到还与器件结合的通道的深度的水平面下，形成并入器件的浅沟槽隔离结构。 然后将设置在光致抗蚀剂插塞下方的沟槽内的氮化物衬垫凹入到基本上等于光致抗蚀剂材料的水平的水平，然后将其除去。 该方法还包括在沟槽内沉积氧化物填充物，从而封装凹陷的氮化物衬垫。

公开(公告)号：US06831347B1

公开(公告)日：2004-12-14

申请号：US08932228

申请日：1997-09-17

申请人： Klaus F. Schuegraf ,  Aftab Ahmad

发明人： Klaus F. Schuegraf ,  Aftab Ahmad

IPC分类号： H01L2900

CPC分类号： H01L21/76224 ,  Y10S148/05

摘要： A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.

摘要翻译： 公开了一种浅沟槽隔离，其中沟槽深度减小到超过现有技术工艺中所达到的深度。 减小的沟槽深度有助于在沟槽再填充过程期间消除空隙的形成，并且在最终隔离结构中提供更大的平坦度。 通过利用具有低介电常数的再填充介电材料，通过减小沟槽深度实现有效的器件隔离。

公开(公告)号：US06500727B1

公开(公告)日：2002-12-31

申请号：US09957423

申请日：2001-09-21

申请人： Cheng-Ku Chen ,  Fang-Cheng Chen ,  Hun-Jan Tao

发明人： Cheng-Ku Chen ,  Fang-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  Y10S148/05

摘要： A method for forming a trench having upper rounded corners comprising the following steps. A substrate having an oxide layer formed thereover is provided. A hard mask layer is formed over the oxide layer. A patterned patterning layer is formed over the hard mask layer leaving one or more portions of the hard mask layer exposed. The hard mask layer is patterned using the patterned patterning layer as a mask to form a patterned hard mask layer having one or more openings exposing one or more portions of the oxide layer. The patterned patterning layer is removed. The oxide layer is patterned using the patterned hard mask layer as a mask using a first trench etching process to etch through the oxide layer at the one or more exposed portions of the oxide layer and into the substrate to form one or more shallow trenches within the substrate having upper rounded corners at the respective interfaces between substrate and patterned oxide layer. The substrate is further etched at the one or more shallow trenches using a second trench etching process to form one or more completed trenches having the upper rounded corners at the respective interfaces between substrate and patterned oxide layer.

摘要翻译： 一种用于形成具有上圆角的沟槽的方法，包括以下步骤。 提供了具有形成在其上的氧化物层的衬底。 在氧化物层上形成硬掩模层。 在硬掩模层之上形成图案化图案层，留下硬掩模层的一个或多个部分露出。 使用图案化图案化层作为掩模对硬掩模层进行构图，以形成具有暴露氧化物层的一个或多个部分的一个或多个开口的图案化硬掩模层。 去除图案化图案层。 使用第一沟槽蚀刻工艺，使用图案化的硬掩模层作为掩模来对氧化物层进行图案化，以蚀刻通过氧化物层的一个或多个暴露部分处的氧化物层并进入衬底，以在衬底内形成一个或多个浅沟槽 衬底在衬底和图案化氧化物层之间的相应界面处具有上圆角。 使用第二沟槽蚀刻工艺在一个或多个浅沟槽处进一步蚀刻衬底，以形成在衬底和图案化氧化物层之间的相应界面处具有上圆角的一个或多个完成的沟槽。

公开(公告)号：US06391746B1

公开(公告)日：2002-05-21

申请号：US09544342

申请日：2000-04-06

申请人： Fernando Gonzalez ,  Jeffrey W. Honeycutt

发明人： Fernando Gonzalez ,  Jeffrey W. Honeycutt

IPC分类号： H01L21322

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/3221 ,  H01L29/32 ,  Y10S148/05 ,  Y10S148/06 ,  Y10S257/913

摘要： In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, the background region being doped with a first-type conductivity enhancing dopant, the first-type conductivity enhancing dopant being either n-type or p-type; c) implanting a second-type conductivity enhancing dopant into the background region to form a second-type implant region entirely contained within the background region, the second-type conductivity enhancing dopant being of an opposite type than the first-type conductivity enhancing dopant of the background region; and d) implanting a neutral-conductivity-type conductivity enhancing dopant into the second-type implant region to form a metals gettering damage region entirely contained within the second-type implant region. The invention also pertains to gettering region structures.

公开(公告)号：US06221560B1

公开(公告)日：2001-04-24

申请号：US09373244

申请日：1999-08-12

申请人： Choi Pheng Soo ,  Lap Chan

发明人： Choi Pheng Soo ,  Lap Chan

IPC分类号： G03C500

CPC分类号： H01L21/31053 ,  Y10S148/05

摘要： A new method for planarizing silicon dioxide surfaces in semiconductor structures. Starting with a structure of an underlying layer (for instance a layer of metal lines) a layer of oxide is deposited and profiled by positive tone imaging. A layer of PPMS is deposited. Using the mask of the starting structure, the PPMS layer is exposed changing the PPMS to PPMSO in the exposed regions. The unexposed PPMS is removed, the PPMSO (unexposed regions of the PPMS) are planarized, this planarization can proceed to the point where no more PPMSO is present (the PPMSO “columns” are removed together with the intra-layer of patterned oxide). The surface thus created shows excellent planarity, this surface can be further planarized down to the top level of the underlying pattern, if it is desirable to do so.

摘要翻译： 一种在半导体结构中平坦化二氧化硅表面的新方法。 从底层（例如一层金属线）的结构开始，通过正色成像沉积和分析氧化层。 存放一层PPMS。 使用起始结构的掩模，PPMS层暴露在暴露区域中将PPMS改变为PPMSO。 去除未曝光的PPMS，PPMSO（PPMS的未曝光区域）被平坦化，该平面化可以进行到不再存在PPMSO的点（与图案化氧化物层内的PPMSO“列”一起被去除）。 如此创建的表面显示出优异的平面度，如果希望这样做，则该表面可以进一步平坦化到底层图案的顶层。

公开(公告)号：US06184127B2

公开(公告)日：2001-02-06

申请号：US09243220

申请日：1999-02-01

申请人： Trung Tri Doan ,  Charles H. Dennison

发明人： Trung Tri Doan ,  Charles H. Dennison

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/76224 ,  H01L21/76802 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/05 ,  H01L2924/00

摘要： A semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass includes, a) forming a field isolation mass within a semiconductor substrate by a trench and refill technique, and a substrate masking layer over the substrate adjacent the field isolation mass, the field isolation mass being capped with an etch stop cap, the field isolation mass having a sidewall covered by the masking layer; b) removing the substrate masking layer away from the isolation mass to expose at least a portion of the isolation mass sidewall; c) forming an etch stop cover over the exposed isolation mass sidewall; d) forming an insulating layer over the isolation mass and substrate area adjacent the isolation mass; and e) etching a contact opening through the insulating layer to adjacent the isolation mass selectively relative to the isolation mass etch stop cap and cover. A semiconductor structure is also described.

摘要翻译： 在与场隔离物质相邻的区域形成接触开口的半导体处理方法包括：a）通过沟槽和再填充技术在半导体衬底内形成场隔离块，以及在与衬底相邻的场隔离质量 所述场隔离物质被蚀刻停止盖封盖，所述场隔离块具有由所述掩蔽层覆盖的侧壁; b）将所述衬底掩模层从所述隔离块上移除以暴露所述隔离质量侧壁的至少一部分; c）在暴露的隔离质量侧壁上形成蚀刻停止盖; d）在邻近隔离块的隔离物质和衬底区域上形成绝缘层; 以及e）相对于所述隔离质量蚀刻停止盖和盖选择性地蚀刻通过所述绝缘层的接触开口以与所述隔离质量相邻。 还描述了半导体结构。

公开(公告)号：US6143623A

公开(公告)日：2000-11-07

申请号：US468224

申请日：1999-12-20

申请人： Nobuyuki Tsuda ,  Hideki Fujikake

发明人： Nobuyuki Tsuda ,  Hideki Fujikake

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L29/78

CPC分类号： H01L21/76224 ,  Y10S148/05

摘要： A semiconductor device includes a semiconductor substrate in which a trench for element isolation is formed, and an element isolation oxide film buried into the trench in such a manner that the element isolation oxide film is projected from the surface of the semiconductor substrate. The element isolation oxide film which is an element isolation insulating film for defining an element forming region on the semiconductor substrate has a projection portion above the surface of the semiconductor substrate. The projection portion has the width wider than that of the trench. The projection portion and a contact portion made in contact with the semiconductor substrate within the trench are made of thermal oxide films, and a portion other than the projection portion and the contact portion is made of a CVD dioxide film.

摘要翻译： 半导体器件包括其中形成用于元件隔离的沟槽的半导体衬底和以从元件隔离氧化膜从半导体衬底的表面突出的方式埋入沟槽中的元件隔离氧化膜。 作为用于限定半导体衬底上的元件形成区域的元件隔离绝缘膜的元件隔离氧化膜在半导体衬底的表面上方具有突起部。 突出部的宽度比沟槽宽。 与沟槽内的半导体衬底接触的突出部分和接触部分由热氧化膜制成，并且突出部分和接触部分之外的部分由CVD二氧化物膜制成。

公开(公告)号：US6118168A

公开(公告)日：2000-09-12

申请号：US997247

申请日：1997-12-23

申请人： Peter K. Moon ,  David T. Krick ,  Kerry L. Spurgin

发明人： Peter K. Moon ,  David T. Krick ,  Kerry L. Spurgin

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  Y10S148/05

摘要： A method of forming a trench isolation structure in a semiconductor substrate. After etching a trench into the semiconductor substrate, an oxide layer is formed within the trench. The surface of this oxide layer is subject to a nitrogen plasma. Subsequently, another oxide layer is deposited over the nitrogen-rich surface of the first oxide layer. Deposition of this second oxide layer is accomplished by a chemical vapor deposition (CVD) process primarily using a reactant gas other than ozone.

摘要翻译： 一种在半导体衬底中形成沟槽隔离结构的方法。 在将沟槽蚀刻到半导体衬底中之后，在沟槽内形成氧化物层。 该氧化物层的表面经受氮等离子体。 随后，在第一氧化物层的富氮表面上沉积另一氧化物层。 通过主要使用除臭氧以外的反应物气体的化学气相沉积（CVD）工艺来实现该第二氧化物层的沉积。

公开(公告)号：US6090684A

公开(公告)日：2000-07-18

申请号：US363184

申请日：1999-07-29

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L29/78

CPC分类号： H01L21/76232 ,  Y10S148/05

摘要： A shallow groove isolation structure (SGI) electrically insulates adjoining transistors on a semiconductor substrate. A pad oxide film is formed on the semiconductor substrate and an oxidation inhibition film is formed on the pad oxide film. Parts of the oxide inhibition film and pad oxide film are removed to form the groove. In particular, the pad oxide film is removed from an upper edge of the groove within a range of 5 to 40 nm. A region of the groove is oxidized in an oxidation environment with a cast ratio of hydrogen (H.sub.2) to oxygen (O.sub.2) being less than or equal to 0.5. At this ratio, the oxidizing progresses under low stress at the upper groove edges of the substrate thereby enabling rounding of the upper groove edges without creating a level difference at or near the upper groove edge on the substrate surface.

摘要翻译： 浅沟隔离结构（SGI）使半导体衬底上的相邻晶体管电绝缘。 在半导体基板上形成衬垫氧化膜，在衬垫氧化膜上形成氧化抑制膜。 除去氧化物抑制膜和垫氧化膜的一部分以形成槽。 特别地，在5〜40nm的范围内，从槽的上边缘去除衬垫氧化膜。 凹槽的区域在氢（H 2）与氧（O 2）的铸造比小于或等于0.5的氧化环境中被氧化。 在该比例下，在基板的上槽边缘处的低应力下氧化进行，从而能够在上槽边缘的四舍五入，而不会在基板表面上的上槽边缘处或附近产生水平差。