公开(公告)号：US09334583B2

公开(公告)日：2016-05-10

申请号：US13202944

申请日：2011-06-27

Applicant: Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

Inventor： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

IPC: C30B25/02 ,  C30B25/18 ,  C30B29/06 ,  C30B23/02 ,  H01L21/02

CPC classification number: C30B25/186 ,  C30B23/025 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02661

Abstract: An epitaxial growth method for preventing auto-doping effect is presented. This method starts with the removal of impurities from the semiconductor substrate and the reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling. This method can prevent auto-doping effect during the epitaxial growth on semiconductor substrate and thus ensure the performance and enhance the reliability of the devices in peripheral circuit region.

Abstract translation: 提出了一种防止自动掺杂效应的外延生长方法。 该方法首先从要使用的半导体衬底和反应室中除去杂质。 然后，在从半导体衬底的表面脱离的掺杂剂原子的提取之前，将半导体衬底装载在清洁的反应室中，以在真空条件下预烘烤。 接下来，在高温低气流条件下，在所述半导体衬底的表面上形成第一本征外延层。 接下来，在低温和高气体流动条件下，在生长的本征外延层的结构表面上形成所需厚度的第二外延层。 最后，冷却后硅片卸载。 该方法可以防止在半导体衬底上的外延生长期间的自掺杂效应，从而确保外围电路区域中器件的性能和可靠性。

公开(公告)号：US20130189799A1

公开(公告)日：2013-07-25

申请号：US13203135

申请日：2011-06-23

Applicant: Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

Inventor： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

IPC: H01L21/762

CPC classification number: H01L21/76205 ,  H01L21/76224 ,  H01L27/0814

Abstract: The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches. This invention can be used for diode-driven, high-density, large-capacity memory, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory; the method thereof is completely compatible with conventional complementary metal-oxide semiconductor (CMOS) process, and because the diode arrays can be formed before the formation of peripheral circuits, no drift of peripheral circuits will be caused by the thermal process thereof, thereby solving the technical challenge of fabricating high-density, large-capacity embedded phase change random access memory.

Abstract translation: 本发明公开了一种制造双沟槽隔离外延二极管阵列的方法。 该方法开始于在衬底上形成重掺杂的第一导电类型区域和重掺杂的第二导电类型区域，随后进行外延生长，然后通过深沟槽蚀刻形成二极管阵列字线之间的隔离，并形成 通过浅沟槽蚀刻垂直于深沟槽的位线之间的隔离，最后通过离子注入由深和浅沟槽隔离所包围的区域中形成分离的二极管阵列单元。 本发明还提供了一种防止由前述的双浅沟槽隔离的外延二极管阵列的相邻字线和位线之间的串扰电流的方法。 本发明可用于二极管驱动，高密度，大容量存储器，如相变随机存取存储器，电阻存储器，磁存储器和铁电存储器; 其方法与常规的互补金属氧化物半导体（CMOS）工艺完全兼容，并且由于可以在外围电路形成之前形成二极管阵列，所以不会由于其热处理而引起外围电路的漂移，从而解决了 制造高密度，大容量嵌入式相变随机存取存储器的技术挑战。

公开(公告)号：US08586405B2

公开(公告)日：2013-11-19

申请号：US13369738

申请日：2012-02-09

Applicant: Chao Zhang ,  Guanping Wu ,  Bo Liu ,  Zhitang Song

Inventor： Chao Zhang ,  Guanping Wu ,  Bo Liu ,  Zhitang Song

IPC: H01L29/02

CPC classification number: H01L27/1021 ,  H01L21/74 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/861

Abstract: A method of manufacturing a semiconductor device and a semiconductor device made by the method is disclosed. The method comprises forming a buried N+ layer in an upper portion of a P-type substrate; performing ion implantation on the buried N+ layer; annealing the buried N+ layer; forming an epitaxial semiconductor layer on the buried N+ layer through epitaxial deposition, wherein, an upper portion of said epitaxial semiconductor layer and a portion underlying said P+ region of said epitaxial semiconductor layer are doped to form a P+ region and an N− region, respectively. Increasing the ion implant dosage of the BNL layer, adjusting the method of annealing the BNL layer to increase the width of the BNL layer, or increasing the thickness of the EPI layer, reduces the vertical BJT current gain and suppressed the substrate leakage current.

Abstract translation: 公开了一种通过该方法制造半导体器件和半导体器件的方法。 该方法包括在P型衬底的上部形成掩埋的N +层; 对掩埋的N +层进行离子注入; 退火埋N +层; 通过外延沉积在掩埋的N +层上形成外延半导体层，其中，所述外延半导体层的上部和所述外延半导体层的所述P +区下面的部分被掺杂以分别形成P +区和N区 。 增加BNL层的离子注入剂量，调整BNL层的退火方法以增加BNL层的宽度或增加EPI层的厚度，减小垂直BJT电流增益并抑制衬底漏电流。

公开(公告)号：US20130134381A1

公开(公告)日：2013-05-30

申请号：US13369738

申请日：2012-02-09

Applicant: CHAO ZHANG ,  GUANPING WU ,  BO LIU ,  ZHITANG SONG

Inventor： CHAO ZHANG ,  GUANPING WU ,  BO LIU ,  ZHITANG SONG

IPC: H01L45/00 ,  H01L21/8239

CPC classification number: H01L27/1021 ,  H01L21/74 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/861

Abstract: A method of manufacturing a semiconductor device and a semiconductor device made by the method is disclosed. The method comprises forming a buried N+ layer in an upper portion of a P-type substrate; performing ion implantation on the buried N+ layer; annealing the buried N+ layer; forming an epitaxial semiconductor layer on the buried N+ layer through epitaxial deposition, wherein, an upper portion of said epitaxial semiconductor layer and a portion underlying said P+ region of said epitaxial semiconductor layer are doped to form a P+ region and an N− region, respectively. Increasing the ion implant dosage of the BNL layer, adjusting the method of annealing the BNL layer to increase the width of the BNL layer, or increasing the thickness of the EPI layer, reduces the vertical BJT current gain and suppressed the substrate leakage current.

Abstract translation: 公开了一种通过该方法制造半导体器件和半导体器件的方法。 该方法包括在P型衬底的上部形成掩埋的N +层; 对掩埋的N +层进行离子注入; 退火埋N +层; 通过外延沉积在掩埋的N +层上形成外延半导体层，其中，所述外延半导体层的上部和所述外延半导体层的所述P +区下面的部分被掺杂以分别形成P +区和N区 。 增加BNL层的离子注入剂量，调整BNL层的退火方法以增加BNL层的宽度或增加EPI层的厚度，减小垂直BJT电流增益并抑制衬底漏电流。

公开(公告)号：US08476085B1

公开(公告)日：2013-07-02

申请号：US13203135

申请日：2011-06-23

Applicant: Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

Inventor： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

IPC: H01L21/00

CPC classification number: H01L21/76205 ,  H01L21/76224 ,  H01L27/0814

Abstract: The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches. This invention can be used for diode-driven, high-density, large-capacity memory, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory; the method thereof is completely compatible with conventional complementary metal-oxide semiconductor (CMOS) process, and because the diode arrays can be formed before the formation of peripheral circuits, no drift of peripheral circuits will be caused by the thermal process thereof, thereby solving the technical challenge of fabricating high-density, large-capacity embedded phase change random access memory.

Abstract translation: 本发明公开了一种制造双沟槽隔离外延二极管阵列的方法。 该方法开始于在衬底上形成重掺杂的第一导电类型区域和重掺杂的第二导电类型区域，随后进行外延生长，然后通过深沟槽蚀刻形成二极管阵列字线之间的隔离，并形成 通过浅沟槽蚀刻垂直于深沟槽的位线之间的隔离，最后通过离子注入由深和浅沟槽隔离所包围的区域中形成分离的二极管阵列单元。 本发明还提供了一种防止由前述的双浅沟槽隔离的外延二极管阵列的相邻字线和位线之间的串扰电流的方法。 本发明可用于二极管驱动，高密度，大容量存储器，如相变随机存取存储器，电阻存储器，磁存储器和铁电存储器; 其方法与常规的互补金属氧化物半导体（CMOS）工艺完全兼容，并且由于可以在外围电路形成之前形成二极管阵列，所以不会由于其热处理而引起外围电路的漂移，从而解决了 制造高密度，大容量嵌入式相变随机存取存储器的技术挑战。

公开(公告)号：US20130145984A1

公开(公告)日：2013-06-13

申请号：US13202944

申请日：2011-06-27

Applicant: Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang

Inventor： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang

IPC: C30B25/18 ,  C30B23/02

CPC classification number: C30B25/186 ,  C30B23/025 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02661

Abstract: This invention relates to a method of epitaxial growth effectively preventing auto-doping effect. This method starts with the removal of impurities from the semiconductor substrate having heavily-doped buried layer region and from the inner wall of reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions so as to remove moisture and oxide from the surface of said semiconductor substrate before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate where the dopant atoms have been extracted out. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling. This method can prevent auto-doping effect during the epitaxial growth on semiconductor substrate and thus ensure the performance and enhance the reliability of the devices in peripheral circuit region.

Abstract translation: 本发明涉及一种有效防止自掺杂效应的外延生长方法。 该方法首先从具有重掺杂掩埋层区域的半导体衬底和要使用的反应室的内壁去除杂质。 然后将半导体衬底装载在清洁的反应室中，以在真空条件下进行预烘烤，以便在从半导体衬底的表面脱附的掺杂剂原子提取之前从所述半导体衬底的表面去除水分和氧化物。 接下来，在高温低气体流动条件下，在所述半导体衬底的已经提取出掺杂剂原子的表面上形成第一本征外延层。 接下来，在低温和高气体流动条件下，在生长的本征外延层的结构表面上形成所需厚度的第二外延层。 最后，冷却后硅片卸载。 该方法可以防止在半导体衬底上的外延生长期间的自掺杂效应，从而确保外围电路区域中器件的性能和可靠性。