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    Method of preventing auto-doping during epitaxial layer growth by cleaning the reaction chamber with hydrogen chloride
    1.
    发明授权
    Method of preventing auto-doping during epitaxial layer growth by cleaning the reaction chamber with hydrogen chloride 有权
    通过用氯化氢清洗反应室来防止外延层生长期间的自掺杂的方法

    公开(公告)号：US09334583B2

    公开(公告)日：2016-05-10

    申请号：US13202944

    申请日：2011-06-27

    申请人： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

    发明人： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

    IPC分类号： C30B25/02 ,  C30B25/18 ,  C30B29/06 ,  C30B23/02 ,  H01L21/02

    CPC分类号： C30B25/186 ,  C30B23/025 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02661

    摘要： An epitaxial growth method for preventing auto-doping effect is presented. This method starts with the removal of impurities from the semiconductor substrate and the reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling. This method can prevent auto-doping effect during the epitaxial growth on semiconductor substrate and thus ensure the performance and enhance the reliability of the devices in peripheral circuit region.

    摘要翻译： 提出了一种防止自动掺杂效应的外延生长方法。 该方法首先从要使用的半导体衬底和反应室中除去杂质。 然后，在从半导体衬底的表面脱离的掺杂剂原子的提取之前，将半导体衬底装载在清洁的反应室中，以在真空条件下预烘烤。 接下来，在高温低气流条件下，在所述半导体衬底的表面上形成第一本征外延层。 接下来，在低温和高气体流动条件下，在生长的本征外延层的结构表面上形成所需厚度的第二外延层。 最后，冷却后硅片卸载。 该方法可以防止在半导体衬底上的外延生长期间的自掺杂效应，从而确保外围电路区域中器件的性能和可靠性。

    METHOD OF FABRICATING DUAL TRENCH ISOLATED EPITAXIAL DIODE ARRAY
    2.
    发明申请
    METHOD OF FABRICATING DUAL TRENCH ISOLATED EPITAXIAL DIODE ARRAY 有权
    双层分离分离的外延二极体阵列的方法

    公开(公告)号：US20130189799A1

    公开(公告)日：2013-07-25

    申请号：US13203135

    申请日：2011-06-23

    申请人： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

    发明人： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76205 ,  H01L21/76224 ,  H01L27/0814

    摘要： The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches. This invention can be used for diode-driven, high-density, large-capacity memory, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory; the method thereof is completely compatible with conventional complementary metal-oxide semiconductor (CMOS) process, and because the diode arrays can be formed before the formation of peripheral circuits, no drift of peripheral circuits will be caused by the thermal process thereof, thereby solving the technical challenge of fabricating high-density, large-capacity embedded phase change random access memory.

    摘要翻译： 本发明公开了一种制造双沟槽隔离外延二极管阵列的方法。 该方法开始于在衬底上形成重掺杂的第一导电类型区域和重掺杂的第二导电类型区域，随后进行外延生长，然后通过深沟槽蚀刻形成二极管阵列字线之间的隔离，并形成 通过浅沟槽蚀刻垂直于深沟槽的位线之间的隔离，最后通过离子注入由深和浅沟槽隔离所包围的区域中形成分离的二极管阵列单元。 本发明还提供了一种防止由前述的双浅沟槽隔离的外延二极管阵列的相邻字线和位线之间的串扰电流的方法。 本发明可用于二极管驱动，高密度，大容量存储器，如相变随机存取存储器，电阻存储器，磁存储器和铁电存储器; 其方法与常规的互补金属氧化物半导体（CMOS）工艺完全兼容，并且由于可以在外围电路形成之前形成二极管阵列，所以不会由于其热处理而引起外围电路的漂移，从而解决了 制造高密度，大容量嵌入式相变随机存取存储器的技术挑战。

    Method of fabricating dual trench isolated epitaxial diode array
    3.
    发明授权
    Method of fabricating dual trench isolated epitaxial diode array 有权
    制造双沟槽隔离外延二极管阵列的方法

    公开(公告)号：US08476085B1

    公开(公告)日：2013-07-02

    申请号：US13203135

    申请日：2011-06-23

    申请人： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

    发明人： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang ,  Zhifeng Xie

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76205 ,  H01L21/76224 ,  H01L27/0814

    摘要： The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches. This invention can be used for diode-driven, high-density, large-capacity memory, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory; the method thereof is completely compatible with conventional complementary metal-oxide semiconductor (CMOS) process, and because the diode arrays can be formed before the formation of peripheral circuits, no drift of peripheral circuits will be caused by the thermal process thereof, thereby solving the technical challenge of fabricating high-density, large-capacity embedded phase change random access memory.

    摘要翻译： 本发明公开了一种制造双沟槽隔离外延二极管阵列的方法。 该方法开始于在衬底上形成重掺杂的第一导电类型区域和重掺杂的第二导电类型区域，随后进行外延生长，然后通过深沟槽蚀刻形成二极管阵列字线之间的隔离，并形成 通过浅沟槽蚀刻垂直于深沟槽的位线之间的隔离，最后通过离子注入由深和浅沟槽隔离所包围的区域中形成分离的二极管阵列单元。 本发明还提供了一种防止由前述的双浅沟槽隔离的外延二极管阵列的相邻字线和位线之间的串扰电流的方法。 本发明可用于二极管驱动，高密度，大容量存储器，如相变随机存取存储器，电阻存储器，磁存储器和铁电存储器; 其方法与常规的互补金属氧化物半导体（CMOS）工艺完全兼容，并且由于可以在外围电路形成之前形成二极管阵列，所以不会由于其热处理而引起外围电路的漂移，从而解决了 制造高密度，大容量嵌入式相变随机存取存储器的技术挑战。

    METHOD OF EPITAXIAL GROWTH EFFECTIVELY PREVENTING AUTO-DOPING EFFECT
    4.
    发明申请
    METHOD OF EPITAXIAL GROWTH EFFECTIVELY PREVENTING AUTO-DOPING EFFECT 有权
    有效防止自动排污效果的外源生长方法

    公开(公告)号：US20130145984A1

    公开(公告)日：2013-06-13

    申请号：US13202944

    申请日：2011-06-27

    申请人： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang

    发明人： Chao Zhang ,  Zhitang Song ,  Xudong Wan ,  Bo Liu ,  Guanping Wu ,  Ting Zhang ,  Zuoya Yang

    IPC分类号： C30B25/18 ,  C30B23/02

    CPC分类号： C30B25/186 ,  C30B23/025 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02661

    摘要： This invention relates to a method of epitaxial growth effectively preventing auto-doping effect. This method starts with the removal of impurities from the semiconductor substrate having heavily-doped buried layer region and from the inner wall of reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions so as to remove moisture and oxide from the surface of said semiconductor substrate before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate where the dopant atoms have been extracted out. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling. This method can prevent auto-doping effect during the epitaxial growth on semiconductor substrate and thus ensure the performance and enhance the reliability of the devices in peripheral circuit region.

    摘要翻译： 本发明涉及一种有效防止自掺杂效应的外延生长方法。 该方法首先从具有重掺杂掩埋层区域的半导体衬底和要使用的反应室的内壁去除杂质。 然后将半导体衬底装载在清洁的反应室中，以在真空条件下进行预烘烤，以便在从半导体衬底的表面脱附的掺杂剂原子提取之前从所述半导体衬底的表面去除水分和氧化物。 接下来，在高温低气体流动条件下，在所述半导体衬底的已经提取出掺杂剂原子的表面上形成第一本征外延层。 接下来，在低温和高气体流动条件下，在生长的本征外延层的结构表面上形成所需厚度的第二外延层。 最后，冷却后硅片卸载。 该方法可以防止在半导体衬底上的外延生长期间的自掺杂效应，从而确保外围电路区域中器件的性能和可靠性。

    Semiconductor device manufacturing method
    5.
    发明授权
    Semiconductor device manufacturing method 有权
    半导体器件制造方法

    公开(公告)号：US08586405B2

    公开(公告)日：2013-11-19

    申请号：US13369738

    申请日：2012-02-09

    申请人： Chao Zhang ,  Guanping Wu ,  Bo Liu ,  Zhitang Song

    发明人： Chao Zhang ,  Guanping Wu ,  Bo Liu ,  Zhitang Song

    IPC分类号： H01L29/02

    CPC分类号： H01L27/1021 ,  H01L21/74 ,  H01L27/2409 ,  H01L29/66136 ,  H01L29/861

    摘要： A method of manufacturing a semiconductor device and a semiconductor device made by the method is disclosed. The method comprises forming a buried N+ layer in an upper portion of a P-type substrate; performing ion implantation on the buried N+ layer; annealing the buried N+ layer; forming an epitaxial semiconductor layer on the buried N+ layer through epitaxial deposition, wherein, an upper portion of said epitaxial semiconductor layer and a portion underlying said P+ region of said epitaxial semiconductor layer are doped to form a P+ region and an N− region, respectively. Increasing the ion implant dosage of the BNL layer, adjusting the method of annealing the BNL layer to increase the width of the BNL layer, or increasing the thickness of the EPI layer, reduces the vertical BJT current gain and suppressed the substrate leakage current.

    摘要翻译： 公开了一种通过该方法制造半导体器件和半导体器件的方法。 该方法包括在P型衬底的上部形成掩埋的N +层; 对掩埋的N +层进行离子注入; 退火埋N +层; 通过外延沉积在掩埋的N +层上形成外延半导体层，其中，所述外延半导体层的上部和所述外延半导体层的所述P +区下面的部分被掺杂以分别形成P +区和N区 。 增加BNL层的离子注入剂量，调整BNL层的退火方法以增加BNL层的宽度或增加EPI层的厚度，减小垂直BJT电流增益并抑制衬底漏电流。

    Hand stand
    7.
    外观设计
    Hand stand 有权

    公开(公告)号：USD968138S1

    公开(公告)日：2022-11-01

    申请号：US29832941

    申请日：2022-03-31

    申请人： Chao Zhang

    设计人： Chao Zhang

    GAME THEORY MODEL FOR PATROLLING AN AREA THAT ACCOUNTS FOR DYNAMIC UNCERTAINTY
    10.
    发明申请
    GAME THEORY MODEL FOR PATROLLING AN AREA THAT ACCOUNTS FOR DYNAMIC UNCERTAINTY 审中-公开
    用于计算动态不确定性帐户的游戏理论模型

    公开(公告)号：US20140279818A1

    公开(公告)日：2014-09-18

    申请号：US14216449

    申请日：2014-03-17

    申请人： Albert Xin Jiang ,  Zhengyu Yin ,  Chao Zhang ,  Milind Tambe ,  Sarit Kraus

    发明人： Albert Xin Jiang ,  Zhengyu Yin ,  Chao Zhang ,  Milind Tambe ,  Sarit Kraus

    IPC分类号： G06N5/04

    CPC分类号： G06N5/048 ,  G06N7/005 ,  G06Q10/047

    摘要： Game theory models may be used for producing a strategy and schedule for patrolling an area like a rail transportation system. In some instances, the model may account for events that cause a patrol unit to deviate from a patrol schedule and route. For example, a patrol schedule may be generated for one or more patrol units using a Bayesian Stackelberg game theory model based on a map of the public transportation system, a schedule of the transports, a list of the one or more patrolling units, a probability distribution for the occurrence of the passenger not paying to ride the transports, a list of the one or more possible events that would delay the patrol units, and a probability distribution for the occurrence of the one or more possible events that would delay the patrolling units represented by a Markov-decision process.

    摘要翻译： 游戏理论模型可用于制定巡视像铁路运输系统这样的区域的战略和时间表。 在某些情况下，该模型可能会导致巡视单位偏离巡逻进度和路线的事件。 例如，可以使用基于公共交通系统的地图，运输时间表，一个或多个巡逻单元的列表，一个或多个巡逻单元的列表，使用贝叶斯Stackelberg游戏理论模型来生成针对一个或多个巡逻单元的巡逻时间表 分配用于不支付乘坐运输工具的乘客的发生，将延迟巡逻单位的一个或多个可能的事件的列表，以及发生一个或多个可能的事件的概率分布，这些事件将延迟巡逻单位 由马尔科夫决定过程代表。